I am a Professor in the Department of Electrical and Computer Engineering at the University of British Columbia in Vancouver, British Columbia, Canada.
My research is concerned with programmable chips known as FPGAs, which is short for Field-Programmable Gate Arrays. These are universal chips, capable of emulating any other digital chip. Of course, this emulation capability comes with some overhead in the form of cost and performance -- a key goal of my research is to drive down the cost as well as improve the speed and power dissipation of these chips. I have done this through optimization at various levels including the transistor-level design and architecture (internal organization) of the device, as well as the CAD tools that map circuits into the device.
My latest work focuses improving designer productivity, primarily by making FPGAs easier to use. I'm especially interested in compute-oriented applications. FPGAs have a reputation for being very difficult to "program", particularly among software-oriented designers, the key users in compute-oriented applications. To help, I am a strong advocate for the use of overlay architectures, which are digital circuits built on top of FPGAs that make them easier to program. Overlays are like a new type of FPGA, in that they themselves are programmable, but they are more application-specific and have fewer users, making them unlikely to be built as custom chips. Nevertheless, my research has shown that regular C programs can be easily mapped to processor-like overlays, and they can be accelerated significantly.
I co-founded VectorBlox Computing which was acquired by Microchip in September 2019. At VectorBlox, we designed a vector accelerator system known as the VectorBlox MXP (MatriX Processor) that operates directly on 1D, 2D and 3D tensors. MXP provides four key architectural features that provide gains in efficiency: scratchpad, hardware DMA, sub-word SIMD, and custom instructions. Instead of a traditional named vector register, MXP uses an addressable scratchpad. Being addressable, vectors are simply pointers in C; this allows any number of vectors of arbitrary length to be formed without any internal fragmentation, reduces the need for data duplication and data movement, and allows use of a stack-based ABI for nesting accelerated vector functions. Hardware DMA makes efficient use of a wide, dedicated path to external memory for transfering 1D and 2D tensors and operates concurrently with computation. Sub-word SIMD provides increased parallelism for operations on byte and halfword elements. Custom instructions make it easy to attach highly pipelined hardware into a C-programmed environment, where the hardware design effort focuses on data operations not on data storage/staging/movement (which is left within C). Furthermore, the MXP is fully portable, allowing the use of almost any host processor and almost any C compiler without the need for any compiler modifications. We measured nearly 10,000 times speedup on an N-body physics problem. With this level of acceleration, compiler autovectorization is almost useless because it demands careful planning of code structure and data layout which are best done manually using compiler intrinsics.
My work on interconnect design for FPGAs resulted
in a book, published in November 2003.
I received a
Best Paper
Award at the
2004 IEEE International Conference on Field-Programmable Technology.
My 2001 paper
Using Sparse Crossbars within LUT Clusters
is included as part of FPGA20, the
Top 25 contributions in the First 20 Years
of the International Symposium on FPGAs
between 1992 and 2011.
Some of my past work on multiprocessing can be found at the
University of Toronto.
