The soft vector processor is coded in Verilog HDL, and simulated using ModelSim. Currently we have no compiler for the processor, but we do have an assembler. All the assembly instructions can be found in the Vector ISA specification document. You can find the latest progress and source code of the project below.
These files are preliminary versions of my project files, and should not be directly used or modified at this point. They are provided simply for preliminary evaluation purposes.
The processor uses Altera megafunctions from Stratix III family, and may not compile on other familities of FPGAs.
- Vector ISA specification document revision 0.8
- Vector CPU Verilog source code 0.81 (with UTIIe scalar core) and assembler
- FPGA 2008 paper "Vector Processing as a Soft-core CPU Accelerator"
- Vector CPU SOPC system (0.81) for Stratix 1s40 board (no MAC units)
- Sample benchmark code used to measure the performance of the vector processor
If you find any bugs/problems other than the ones listed here, please email me and tell me about them.
- Processor may not function correctly if the number of vector lanes is not a power of 2
- MemWidth of 32 may have problems executing vector stores (MemWidth of 64, 128 do work)
- Setting a VPU width of 8 may cause compilation errors and may cause the processor to not function correctly
Nov 2, 2008
- Fixed a bug in VPU_controller.v causing the transfer from load buffer to vector register file micro-instruction not to execute
May 9, 2008
- Changed vector lane multiplier behaviour
Apr 26, 2008
- Fixed assembler bug in which vector control register numbers are incorrect for vmstc/vmcts
- Too many changes to processor to list...
Feb 23, 2008
- Fixed a bug in instructions that need to transfer a value from scalar core to vector core
Feb 8, 2008
- Updated CPU source code bundle and vector assembler. Instructions should all work in the current configuration.
- New and improved configuration scripts to configure the processor (see README file).
- New SOPC Builder support (see README file).
- Nios II EDS "hack" to support the processor (see README file).
Jan 8, 2008
- Posted CPU source code bundle including UTIIe scalar core. You should now be able to simulate the complete processor in ModelSim.
- Indexed vector store (vstx) should now work
- Updated ISA specification to update vfand.vs, vfor.vs, vfxor.vs, vfnor.vs instructions (now supported by processor)
Dec 28, 2007
- Posted preliminary vector processor source code (without scalar core as I have not received permission to post it; which unfortunately means you cannot simulate it)
- Updated ISA specification for minor clarification of vfld, vfst instructions
Dec. 25, 2007
- Posted preliminary assembler source code
- Posted preliminary ISA specification
Most Likely Coming Soon
- Verification with different processor parameters
Future Improvements (probably not by me)
- Fully pipeline UTIIe so it issues and executes 1 instruction per cycle (currently issues and completes one instruction every 5 cycles)
- Fixed point support using rounding/saturation feature of Stratix III DSP blocks
- Redesign vector store memory interface to reduce resource usage, perhaps a slower interface
I would like to thank Chris Eagleston for developing the assembler for this architecture, Blair Fort for providing the UTIIe for this research, and Dr. Guy Lemieux for his guidance and supervision on this project. This research is partially funded by NSERC.