Dr.  Andre Ivanov

Education

 Ph.D., McGill University, Montreal, QC, Canada, 1989
 M.Eng., McGill University, Montreal, QC, Canada, 1985
 B.Eng., McGill University, Montreal, QC, Canada, 1983

Research Interests

VLSI, System on Chip, Integrated Circuits, Test, Design for Testability, Built-In Self-Test, Fault Tolerance, Fault-Tolerant Computing, Design for Manufacturability & Yield, Nano-electronics, Microsystems  

VLSI & System on Chip Group

Microsystems and Nanotechnology Research Group

Institute for Computing, Information & Cognitive Systems (ICICS)

Membership & Service

Associate Editor, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems

Associate Editor, IEEE Design and Test of Computers

Associate Editor, Journal of Electronic Testing: Theory and Applications, Elsevier

Member, Board of Governors, IEEE Computer Society

Chair, IEEE Computer Society Test Technology Technical Council (TTTC)

Teaching

Undergraduate

EECE 254: Electronic Circuits

EECE 201 Project Integrated Program I

EECE 202 Project Integrated Program II

EECE 203 Biomedical Engineering Project Integrated Program  

Graduate

EECE 578: Integrated Circuit Design for Test

Graduate Students (Completed & Ongoing degrees)

Journal PUBLICATIONS

1.       A.K.M. K. Mollah, R. Rosales, S.Tabatabaei, J. Cicalo, A. Ivanov, “Design of a Tunable Differential Ring Oscillator with Short Start-Up and Switching Transients, IEEE Trans. on Circuits and Systems I, accepted June 2007.

2.       C. Grecu, A. Ivanov, R. Saleh, P.P. Pande, ”Testing Network on Chip Communication Fabrics”, IEEE Trans. on CAD, accepted June 2007, 20 formatted pages.

3.       Q. Xu, B. Wang, A. Ivanov, E. Young, “Test Scheduling for BISTed Embedded SRAMs with Data Retention Faults”, IET Computers and Digital Techniques (Formally IEE Proceedings), Vol. 1, No. 3, May 2007, pp. 256-264.

4.       Z. Fantai, A. Ivanov, “MPM-Based Interconnect Architecture for the Design of 3D MP-SOCs,” Chinese Journal of Electron Devices, Vol. 30, No. 4, August 2007, pp. 1—4.

5.       H.G. Schulze, R. B. Foist, A. I. Jirasek, A. Ivanov, R.F.B. Turner, “Two-Point Maximum Entropy Noise Discrimination in Spectra Over a Range of Baseline Offsets and Signal-to-Noise Ratios”, Applied Spectroscopy, Vol. 61, No. 2., Feb. 2007, pp. 157 – 164.

6.       Z. Ebadi, A. Nasiri Avanaki, R. Saleh, A. Ivanov, “Design and Implementation of Reconfigurable and Flexible Test Access Mechanism (TAM) for System-on-Chip (SoC)”,  Integration – the VLSI journal, Vol. 40, 2007,  pp. 149 – 160.

7.       (invited) R. Saleh, S. Wilton, S. Mirabbasi, A. Hu, M. Greenstreet, G. Lemieux, P. Pande, C. Grecu, A. Ivanov, System on Chip: Reuse and Integration, Proceedings of the IEEE, Vol. 94, No. 6, June 2006, pp. 1050 -- 1069.

8.       J. Yang, B. Wang, Y. Wu, A. Ivanov, "Fast Detection of Data Retention Faults and Other SRAM Cell Open Defects", IEEE Transactions on Computer Aided Design (TCAD) of Integrated Circuits and Systems, Vol. 25, No. 1, Jan. 2006, pp. 167 – 180.

9.       B. Wang, A. Kuo, T. Farahmand, A. Ivanov, Y. B. Cho, S. Tabatabaei, “A Realistic Timing Test Model and its Applications in High-Speed Interconnect Devices”, Journal of Electronic Testing: Theory and Applications, Vol. 21, 2005, pp. 621 -- 629.

10.   S. Sheikhaei, S. Mirabbasi, A. Ivanov, “A 0.18 um CMOS Pipelined Encoder for a 5 Gb/s 4-bit Flash Analogue-to-Digital Converter,” Can. Journal of Electrical and Computer Engineering, Vol. 30, No. 4, Fall 2005, pp. 183 – 187.

11.   A. Kuo, T. Farahmand, S. Tabatabaei, A. Ivanov, Crosstalk Bounded Uncorrelated Jitter (BUJ) for High-speed Interconnects”, IEEE Trans. on Instrumentation and Measurement, Vol. 54, No. 5, Oct. 2005, pp. 1800—1810.

12.   P. Pande, C. Grecu, A. Ivanov, R. Saleh, G. de Micheli, “Design, Synthesis and Test of Networks on Chip: Challenges and Solutions,” IEEE Design and Test of Computers, Vol. 22, No. 5, Sept/Oct. 2005, pp. 404 – 413.

13.    P. Pande, C. Grecu, M. Jones, A. Ivanov, R. Saleh "Performance Evaluation and Design Trade-offs for Network-on-chip Interconnect Architectures", IEEE Transactions on Computers,  Vol. 54, No. 8, August 2005, pp. 1025 -- 1040.

14.   C. Grecu, P. P. Pande, A. Ivanov, R. Saleh "Timing Analysis of Network on Chip Architectures for MP-SoC Platforms," Microelectronics Journal, Elsevier, Vol. 36, 2005, pp. 833 – 845.

15.   Y. Maidon, T. Zimmer, E. Nold, A. Ivanov, “An Analog Circuit Fault Characterization Methodology”, Journal of Electronic Testing: Theory and Applications, Vol. 21, No. 2, April 2005, pp. 127—134.

16.   M. Nahvi, A. Ivanov, “Indirect Test Architecture for SoC Testing”, IEEE Transactions on Computer Aided Computer Design of Circuits and Systems,  Vol. 23, No. 7, July 2004, pp. 1128 – 1142.

17.   N. Ou, T. Farahmand, A. Kuo, S. Tabatabaei, A. Ivanov, “Jitter Models for the Design and Test of High-Speed Serial Interconnnects”, IEEE Design & Test of Computers, Vol. 21, No. 4, July/August 2004, pp. 302 – 313.

18.   J. Altet, M.A. Salhi, S. Dilhaire, A. Syal, A. Ivanov, “Calibration-Free Heat Source Localization in ICs Entirely Covered by Metal Layers”, IEE Electronics Letters, 19 February 2004, Vol. 40, No. 4, pp. 37-38.

19.   J. Altet, M.A. Salhi, S. Dilhaire, A. Syal and A. Ivanov, "Localisation of devices acting as heat sources in ICs covered entirely by metal layers", IEE Electronics Letters, 2 October 2003, Vol. 39, No. 20, pp. 1440 – 1441.

20.   J. Altet, A. Ivanov, A. Wong, "Thermal Testing of Analogue Integrated Circuits: A Case Study," Journal of Electronic Testing: Theory and Applications, Vol.  19, pp. 353-357, 2003.

21.   F. Azais, A. Ivanov, M. Renovell, S. Tabatabaei, and Y. Bertrand, "A Unified Digital Test Technique for PLLs to Cover Catastrophic Faults", IEEE Design and Test of Computers, Vol. 20, No. 1, Jan./Feb. 2003, pp. 60 – 67.

22.   S. Tabatabaei and A. Ivanov, “Embedded Timing Analysis: A SoC Infrastructure”, IEEE Design and Test of Computers, Vol. 19, No. 3, May-June 2002, pp. 24 – 36.

23.   Z. Zhao, A. Ivanov, “Embedded Servo Loop for ADC Linearity Testing”, Microelectronic Journal, Elsevier, Vol. 33, 2002, pp. 773 — 780.

24.   A. Syal, V. Lee, A. Ivanov, J. Altet, “CMOS Differential and Absolute Thermal Sensors”, Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers, Vol. 18, pp. 295—304, 2002.

25.   A. Ivanov, S. Rafiq, M. Renovell, F. Azais, and Y. Bertrand, "On the Detectability of CMOS Floating Gate Transistor Faults," IEEE Trans. Computer Aided Design of Circuits and Systems, Vol. 20, No. 1, Jan. 2001, pp. 116 --128.

26.   A. Ivanov and V. Devdas, "Catastrophic Short and Open Fault Detection in Bipolar CML Circuits: A Case Study,” Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers, Vol. 16, 2000, pp. 631-- 634.

27.   A. Ivanov, B. Tsuji, Y. Zorian, "Programmable Space compactors for BIST", IEEE Transactions on Computers, Vol. 45, No. 12, Dec. 1996, pp. 1393 --1405.

28.   D. Lambidonis, A. Ivanov, V.K. Agarwal, "Fast Signature Computation for BIST Linear Compactors", IEEE Trans. on Computer Aided Design of Circuits and Systems, Vol. 14, No. 8, August 1995, pp. 1037--1044.

29.   Y. Wu, A. Ivanov, "Single Reference Multiple Intermediate Signatures for BIST", IEEE Trans. on Computers, Vol. C-44, No. 6, June 1995, pp. 817-- 825.

30.   Y. Wu, A. Ivanov, "Reducing Hardware with Fuzzy Multiple Signature Analysis", IEEE Design and Test of Computers, Vol. 12, No. 1, Spring 1995, pp. 68--74.

31.   D. Lambidonis, V.K. Agarwal, A. Ivanov, D. Xavier, "A Quasi-Optimal Scheduling of Intermediate Signatures for Multiple Signature Analysis Compaction Testing Schemes", Journal of Electronic Testing (JETTA), Kluwer, Vol. 6, No. 1, Feb. 1995, pp. 75 -- 84.

32.   S. Pilarski, A. Ivanov, T. Kameda, "On Minimizing Aliasing in Scan-Based Compaction", Journal of Electronic Testing (JETTA), Kluwer, Vol. 5, No. 1, Feb. 1994, pp. 83--90.

33.   T. Kameda, S. Pilarski, A. Ivanov, "Notes on Multiple Input Signature Analysis", IEEE Trans. on Computers, Vol. 42, No. 2, Feb. 1993, pp. 228--234.

34.   S. Pilarski, T. Kameda, A. Ivanov, "Sequential Faults and Aliasing", IEEE Trans. on Computer-Aided Design of Circuits and Systems, Vol. 12, No. 7, July 1993, pp. 1068 --1074.

35.   A. Ivanov, S. Pilarski, "Performance of Signature Analysis for Compact IC Testing: A Survey of Bounds, Exact, and Heuristic Algorithms," Integration, The VLSI Journal, Vol. 13, pp. 17-- 38, May 1992.

36.   Y. Wu, A. Ivanov, "A Multiple Signature Compaction Scheme for BIST", Journal of Semicustom ICs, Publisher: Elsevier Advanced Technology, Vol. 23, 1992, pp. 205 --214.

37.   A. Ivanov, Y. Zorian, "Computation of Error Escape Probability in Count-Based Compaction Schemes", IEEE Trans. on Computer-Aided Design of Circuit and Systems, Vol. 11, No. 6, June 1992, pp. 768 --777.

38.   Y. Zorian, A. Ivanov, "An Effective BIST Scheme for ROMs", IEEE Trans. on Computers, Vol. 41, No. 5, May 1992, pp. 646--653.

39.   V.K. Agarwal, A. Ivanov, "Computing the Probability of Undetected Error for Shortened Cyclic Codes," IEEE Trans. on Communications, vol. 40, no. 3, March 1992, pp. 494 -- 499.

40.   A. Ivanov, C.W. Starke, V.K. Agarwal, W. Daehn, M. Gruetzner, T.W. Williams, "Iterative Algorithms for Computing Aliasing Probabilities," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 10, No. 2, Feb. 1991, pp. 260--265.

41.   D. Xavier, R.C. Aitken, A. Ivanov, V.K. Agarwal, "Using an Asymmetric Error Model to Study Aliasing in Signature Analysis Registers", IEEE Trans. on Computer-Aided Design of Circuits & Systems, Vol. 11, No. 1, Jan. 1991, pp. 16 --25.

42.   A. Ivanov, V.K. Agarwal, "An Analysis of the Probabilistic Behaviour of Linear Feedback Signature Registers", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 8, No. 10, Oct. 1989, pp. 1074--1088.

43.   A. Ivanov, V.K. Agarwal, "Dynamic Testability Measures for ATPG", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 7, No. 5, May 1988, pp. 598—608.

CONFERENCE PROCEEDINGS

1.       Z. Fantai, A. Ivanov, “A Third Type of Interconnection Architecture for the Design of 3D MP-SoC”, Proc. 7th International Conference on ASICs (ASICON 2007), Guilin, China, October 2007.

2.       S. Sheikhaei, S. Mirabbasi, A. Ivanov, “A 43mW Single-Channel 4GS/s 4-Bit Flash ADC in 0.18µm CMOS”, Proc. IEEE Custom Integrated Circuits Conference (CICC)”,San Jose, CA, Sept. 2007.

3.       A. Kuo, A. Labun, N. Swart, A. Ivanov, “Crosstalk Timing Model for High-Speed Interconnects with Impedance Discontinuity”, Proc. 11 IEEE Workshop on Signal Propagation on Interconnects, Portofino, Italy, May 2007.

4.       C. Grecu, L. Anghel, P. Pande, A. Ivanov, R. Saleh, “Essential Fault-Tolerance Metrics for NoC Infrastructures”, to appear in Proc. IEEE International On-Line Test Symposium (IOLTS), Hersonissos-Heraklion, Crete, Greece, 9 – 11,  July 2007.

5.       R. Foist, A. Ivanov, and R. Turner, “An FPGA Design Project: Creating a PowerPC Subsystem plus User Logic”, Proc. 2007 International Conference on Microelectronic Systems Education, San Diego, CA, 2 –4 June 2007, 2 pages.

6.       Y. Wu, A. Ivanov,  “Low-Power SoC Memory BIST”, Proc. IEEE 21st International Symp. On Defect and Fault Tolerance in VLSI Systems, Arlington, VA, Oct. 2006, pp. 197 – 205.

7.       C. Grecu, A. Ivanov, R. Saleh, P.P. Pande, “SoC Interconnect Yield Improvement Using Crosspoint Redundancy”, Proc. IEEE 21st International Symp. On Defect and Fault Tolerance in VLSI Systems, Arlington, VA, Oct. 2006, pp. 457—465.

8.       F. Karim, K. Walus, A. Ivanov, “Crosstalk in QCA Arithmetic Circuits,” Proc. of SPIE – Advanced Signal Processing Algorithms, Architectures, and Implementations, XVI”, Vol. 6313, August 2006, pp. 631306-1 – 631306-8.

9.       C.Grecu, A. Ivanov, R. Saleh, E.S. Sogomonyan, P. Pande, "On-line Fault Detection and Location for NoC Interconnects", Proc. 12th IEEE International On-Line Testing Symposium (IOLTS), Como, Italy, 10—12 July 2006, pp. 145 -- 150.

10.   D. Ho, K. Iniewski, S. Kasnavi, A.Ivanov, S. Natarajan, “Ultra-Low Power 90 nm 6T SRAM Cell for Wireless Sensor Network Applications”, Proc. IEEE International Symposium on Circuits and Systems, ISCAS 2006, Greece, May 2006, pp. 4131 – 4134.

11.   C.Grecu, P. Pande, A. Ivanov, R. Saleh, "BIST for Network on Chip Interconnect Infrastructures", Proc. of 24th IEEE VLSI Test Symposium (VTS), Berkeley, CA, 30 April – 4 May 2006, pp. 30 –35.

12.   T. Farahmand, S. Tabatabaei, F. Ben-Zeev, A. Ivanov, “A DDJ Calibration Methodology for High-Speed Test and Measurement Equipment”, Proc. IEEE International Test Conference, Austin, TX, Nov. 2005, Paper 9.3, pp. 1—10.

13.   C. Grecu, P. P. Pande, B. Wang, A. Ivanov, R. Saleh, "Methodologies and Algorithms for Testing Switch-Based NoC Interconnects”, Proc. IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, Monterey, CA, Oct. 2005, pp. 239 -- 246.

14.   P. P. Pande, C. Grecu, M. Jones, A. Ivanov, R. Saleh, "Effect of traffic localization on energy dissipation in NoC-based interconnect infrastructures",  Proc. IEEE International Symposium on Circuits and Systems, ISCAS 2005, Kobe Japan, May 2005, pp. 1774 -- 1777.

15.   S. Sheikhaei, S. Mirabbasi, A. Ivanov, “A 4-bit 5GS/s flash A/D converter in 0.18μm CMOS,” Proc. IEEE International Symposium on Circuits and Systems, Kobe, Japan, May 2005, pp. 6138 -- 6141.

16.   S. Sheikhaei, S. Mirabbasi, A. Ivanov, “A 0.35μm CMOS Comparator Circuit for High-Speed ADC Applications,” Proc. IEEE International Symposium on Circuits and Systems, Kobe, Japan, May 2005, pp. 6134 -- 6137.

17.   S. Sheikhaei, S. Mirabbasi, A. Ivanov, “An Encoder For a 5GS/s 4-Bit Flash ADC in 0.18µm CMOS,”  Proc. 18th  Annual IEEE Canadian Conference on Electrical and Computer Engineering, Saskatoon, Canada, May 2005, pp. 680 -- 683. (Best Student Paper Award)

18.   B. Wang, Y. Wu, J. Yang, A. Ivanov, Y. Zorian, "SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms", Proc. 23rd IEEE VLSI Test Symposium (VTS05), Palm Springs, CA, USA, May 1 – 5 , 2005, pp. 66 -- 71. 

19.   B.  Wang, Y. Wu, A. Ivanov, "A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs", Proc.  Design Automation and Test in Europe (DATE 2005), Munich, Germany, Mar. 7-11, 2005, 6 pages.

20.   B. Wang, J. Yang, Y. Wu, A. Ivanov, “A Retention-Aware Test Power Model for Embedded SRAM, Proc. Asia and South Pacific Design Automation Conference 2005 (ASP-DAC), Shanghai, China, Jan. 18 -21, 2005.

21.   B.  Wang, Y. Wu, A. Ivanov, “Designs for Reducing Test Time of Distributed Small Embedded SRAMs”, Proc. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04), Cannes, France, Oct. 10-17, 2004, pp. 120 – 128.

22.   A. Kuo, T. Farahmand, N. Ou, S. Tabatabaei, A. Ivanov, “Jitter Models and Measurement Methods for High Speed Serial Interconnects”, Proc. IEEE International Test Conference, Charlotte, NC, October 2004, pp. 1295 – 1312.

23.   P. Pande, C. Grecu, M. Jones, A. Ivanov, R. Saleh, “Evaluation of MP-SoC Interconnect Architectures: A Case Study”, Proc. International Workshop on System on Chip for Real-Time Applications”, Banff, July 2004, pp. 253 – 256.

24.   C. Grecu, P. Pande, A. Ivanov, R. Saleh, “Structured Interconnect Architecture: A Solution for the Non-Scalability of Bus-Based SoCs”, Proc. IEEE Great Lakes VLSI Conference, Boston, MA, April 2004, pp. 192 – 195.

25.   B. Wang, J. Yang, J. Cicalo, A. Ivanov, “Reducing Embedded SRAM Test Time under Redundancy Constraints”, Proc. IEEE VLSI Test Symposium, Napa, CA, April 2004, pp. 237 -- 242 .

26.   J. Altet, A. Rubio, A. Salhi, J.L. Gálvez, S. Dilhaire, A. Syal, A. Ivanov, “Sensing Temperature in CMOS circuits for Thermal Testing”, Proc. IEEE VLSI Test Symp., Napa, CA, April 2004, pp 179 -- 184.

27.   C. Grecu, P. Pande, A. Ivanov, R. Saleh, "A Scalable Communication-Centric SoC Interconnect Architecture," Proc. IEEE International Symposium on Quality Electronic Design, ISQED 2004, San Jose, California, USA, 22-24 March 2004, pp. 343--349.

28.   J. Yang, B. Wang, A. Ivanov, "Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test Mode", Proc. 17th International Conference on VLSI Design, Mumbai, India, January 5-9, 2004.

29.   B. Wang, Y. B. Cho, S. Tabatabaei, A. Ivanov, "Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-offs for High-Speed Interconnect Device Testing",  Proc. IEEE Twelfth Asian Test Symposium (ATS'2003), Nov. 17-19, 2003, pp. 348-353.

30.   B. Wang, J. Yang, A. Ivanov, “On the Reduction of Test Time of Embedded SRAMs” Proc. 2003 IEEE International Workshop on Memory Technology, Design and Testing, S. Jose, CA, July 2003, pp. 47 – 52.

31.   P. Pande, C. Grecu, A. Ivanov and R. Saleh, “A Switch Based Interconnect for Future Systems on chip”, Proc. SPIE's International Symposium on Microtechnologies for the New Millennium 2003, Spain, May 2003, pp. 228 – 237.

32.   M. Hamour, R. Saleh, S. Mirabbasi, A.  Ivanov, "Analog IP Design Flow for SoC Applications", Proc. IEEE Int. Symposium on Circuits and Systems, Bangkok, Thailand, Vol. IV, May 2003, pp. 676-679.

33.   P. Pande, C. Grecu, and A. Ivanov, “Design of a Switch for Network on Chip Applications”, Proc. IEEE Symposium on Circuits and Systems, Bangkok, Thailand, May 2003, pp. 217 – 220.

34.   P. Pande, C. Grecu, A. Ivanov and R. Saleh, “High Throughput Switch-Based Interconnect For Future SoCs”, Proc. International Workshop on System on Chip for Real-Time Applications”, Banff, July 2003, pp. 304 – 310.

35.   M. Nahvi and A. Ivanov, “An Embedded Autonomous Scan-Based Results Analyzer (EARA) for SoC Cores”, Proc. IEEE VLSI Test Symposium, Napa, CA, April 2003, pp. 293 – 298.

36.   Z. Sadat Ebadi and A. Ivanov, “Time Division Multiplexed TAM: Comparison and Implementation”, Proc. Design Automation and Test in Europe, Munich, Germany, March 2003, pp. 732 –737.

37.   S. Tabatabaei and A. Ivanov, “An Embedded Core for Sub-Picosecond Timing Measurements”, Proc. IEEE International Test Conference, Baltimore, MD, October 2002, pp. 129 – 137.

38.   M. Nahvi, A. Ivanov, and R. Saleh, “Designated Autonomous Scan-Based Testing (DAST) for Embedded Cores”, Proc. IEEE International Test Conference, Baltimore, MD, October 2002, pp. 1176 – 1183.

39.   L. Hong, M. Nahvi, R. Fung, A. Ivanov, R. Saleh, “Novel Test Methodologies for SoC/IP Design: Implementation and Comparison”, Proc. Int.  Workshop on System on Chip for Real-Time Applications, Banff, July 2002, pp. 20 – 30.

40.   Z.  Sadat Ebadi, A. Ivanov, “Design of an Optimal Test Access Architecture under Power and Place-and-Route Constraints using GA”, Proc. IEEE Latin American Test Workshop, Montevideo, Uruguay, Feb. 2002, pp. 154 – 159.

41.   Z. Sadat Ebadi, A. Ivanov, “Design of an Optimal Test Access Architecture Using a Genetic Algorithm”, Proc. Asian Test Symposium, Kyoto, Japan, Nov. 2001, pp. 205 – 210.

42.   A. Syal, V. Lee, A. Ivanov and J. Altet, “A Differential CMOS Thermal Sensor”, Proc. IEEE International On-Line Test Workshop, Italy, July 2001, pp. 127 – 132.

43.   M. Nahvi and A. Ivanov, “A Packet-Based Test Access Mechanism Scheme for System on Chip”, Proc. IEEE European Test Workshop, Stockholm, Sweden, May 2001, pp. 81 – 86.

44.   P. Chen and A. Ivanov, “Defect-Oriented Testing of an ECL/CMOS Level Converter Circuit”, Proc. 1st IEEE Latin America Test Workshop, Rio de Janeiro, March 2000, pp. 42—46.

45.   M. Renovell, A. Ivanov, F. Azais, Y. Bertrand, S. Rafiq, “Optimal Detection of Floating Gate Transistor Faults”, Proc. International Test Conference, Atlantic City, Sept. 1999, pp. 477--486.

46.   S. Tabatabaei, A. Ivanov, “A Built-In Current Monitor for Testing Analog Circuit Blocks”, Proc. International Symposium on Circuits and Systems, Orlando, FL, May 1999, pp. II-109 -- II-114.

47.   S. Tabatabaei, A. Ivanov, “A Current Integrator for BIST of Mixed-Signal ICs”, Proc. IEEE VLSI Test Symp., Dana Point, CA, April 1999, pp. 311-318.

48.   S. Tabatabaei, A. Ivanov, “A Built-In Current Sensor for Testing Analog Circuit Blocks”, Proc. International Conference on Instrumentation and Measurement, Venice, Italy, May 1999, pp. 1403 - 1408.

49.   S. Rafiq, A. Ivanov, S. Tabatabaei, M. Renovell, “Testing for Floating Gate Defects in CMOS Circuits,” Proc. IEEE Asian Test Symp., Singapore, Dec. 1998, pp. 228-236.

50.   F. Azais, A. Ivanov, M. Renovell, Y. Bertrand, “A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs)”, Proc. IEEE Asian Test Symp., Singapore, Dec. 1998, pp. 383- 387.

51.   V. Devdas, A. Ivanov, “Non-Intrusive Testing of High-Speed CML Circuits”, Proceedings of IEEE Asian Test Symposium, Singapore, Dec. 1998, pp. 172-178.

52.   M. Dalmia, A. Ivanov, S. Tabatabaei, “Power Supply Current Monitoring Techniques for Testing PLLs”, Proc. IEEE Asian Test Symposium, Akita, Japan, Nov. 1997, pp. 366-371.

53.   Bishop, A. Ivanov, "Fault Simulation and Testing of an OTA Biquadratic Filter", Proc. Int. Symp. on Circuits and Systems, April 1995, pp. 1764--1767.

54.   B. Tsuji, A. Ivanov, Y. Zorian, "Selecting Programmable Space Compactors for BIST Using Genetic Algorithms", Proc. IEEE Asian Test Symp., Nara, Japan, Nov. 1994, pp. 233--241.

55.   A. Bishop, A. Ivanov, "On the testability of CMOS Feedback Amplifiers", Proc. IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, Montreal, Quebec, Oct. 1994, pp. 65--74.

56.   Y. Wu, A. Ivanov, "On Achieving Minimal Hardware Multiple Signature Analysis for BIST”, Proc. IEEE Asian Test Symposium, Beijing, Nov. 1993, pp. 311--316.

57.   C. Zhang, Y. Wu, A. Ivanov, "On Fault Coverage in VLSI built-In Self-Test with Multiple Signature Analysis", Proc. 1993 Canadian Conf. on Elec. and Computer Eng., Vancouver, B.C., Sept. 1993, pp. 449--452.

58.   W. Low, A. Ivanov, "An Integrated Functional Tester for CMOS Logic", Proc. 1993 Canadian Conf. on Elec. and Computer Eng., Vancouver, B.C., Sept. 1993, pp. 453--456.

59.   P. Bonek, A. Ivanov, S. Kallel, "A Variable Rate Constraint Length K=5 Viterbi Decoder for 12 Mb/s", Proc. 1993 Canadian Conf. on Elec. and Computer Eng., Vancouver, B.C., Sept. 1993, pp. 582--585.

60.   Y. Zorian, A. Ivanov, "Programmable Space Compacting for BIST", Proc. 23rd  Int. Fault Tolerant Computing Symp., Toulouse, France, June 1993, pp. 340--349.

61.   Y. Wu, A. Ivanov, "Minimal Hardware Multiple Signature Analysis for BIST", Proc. IEEE VLSI Test Symposium, Atlantic City, April 1993, pp. 17--20.

62.   Y. Wu, A. Ivanov, "A Fuzzy Compaction Scheme for BIST", Proc. IEEE Asian Test Symposium, Hiroshima, Japan, Nov. 1992, pp. 247--252.

63.   Y. Wu, A. Ivanov, "A Minimal Hardware Overhead BIST Data Compaction Scheme", Proc. IEEE ASICs Conf, Rochester, NY, Sept. 1992, pp. 358--371.

64.   S. Kallel, V. Leung, A. Ivanov, "Design Framework for a Mobile Data Link Protocol", Proc. International Conf. on Selected Topics in Wireless Communications, June 1992, Vancouver, B.C., pp. 44--47.

65.   Y. Wu, A. Ivanov, "Accelerated Path Delay Fault Simulation", Proc. 10th IEEE VLSI Test Symposium, Atlantic City, April 1992, pp. 1--6.

66.   D. Lambidonis, A. Ivanov, V.K. Agarwal, "Fast Signature Computation For Linear Compactors", Proc. International Test Conf., Nashville, TN, Oct. 1991, pp. 808--817.

67.   Y. Wu, A. Ivanov, "Multiple Signature Compaction Scheme for BIST", Proc. Canadian Conf. on VLSI, Kingston, Ontario, Aug. 1991, pp. 2.2.1--2.2.7.

68.   D. Lambidonis, V.K. Agarwal, A. Ivanov, D. Xavier, "Computation of Exact Fault Coverage For Compact Testing Schemes", Proc. Int. Symposium on Circuits and Systems, Singapore, June 1991, pp. 1873-1876.

69.   Y. Wu, A. Ivanov, "A New Path Delay Fault Simulation Algorithm," Proc. European Test Conference, Munich, April 1991, pp. 504.

70.   A. Ivanov, Y. Zorian, "Computing the Error Escape Probability in Count-Based Compaction Schemes," Proc. Int. Conf. on Computer-Aided Design, Santa Clara, Nov. 1990, pp. 368--371.

71.   Y. Zorian, A. Ivanov, "EEODM: An Effective BIST Scheme for ROMS," Proc. Int. Test Conf., Washington, D.C., Sept. 1990, pp. 871--879, also in Proc. AT & T Test Conf., Princeton, NJ, May 1990, pp. 4.17.1- 4.17.7.

72.   D. Xavier, R.C. Aitken, A. Ivanov, V.K. Agarwal, "Experiments on Aliasing in Signature Analysis Registers", Proc. International Test Conf., Washington, D.C., Aug. 1989, pp. 344--354.

73.   H. Cox, A. Ivanov, V.K. Agarwal, J. Rajski, "On Fault Multiple Fault Coverage and Aliasing Probability Measures", Proc. IEEE International Test Conf., Sept. 1988, pp. 314--321.

74.   A. Ivanov, V.K. Agarwal, "An Iterative Technique for Calculating Aliasing Probability of Linear Feedback Signature Registers", Proc. 18th Int. Symposium on Fault Tolerant Computing, Tokyo, June 1988, pp. 70--75.

75.   A. Ivanov, V.K. Agarwal, "On a Fast Method to Monitor the Behaviour of Signature Analysis Registers", Proc. Int. Test Conf., Washington, D.C., Sept. 1987, pp. 645--65.

76.   A. Ivanov, V.K. Agarwal, "Testability Measures --- What do they do for ATPG?", Proc. Int. Test Conf., Washington, D.C., Sept. 1986, pp. 129--138.

77.   A. Ivanov, M. Peckel, "Application of the NORA Technique in the Design of CMOS Digital Integrated Circuits", Tech. Digest of 1984 Canadian VLSI Conf., Oct. 1984, pp. 2.50--2.53.

PATENTS

1.       S. Tabatabaei and A. Ivanov, “High Resolution Time to Digital Converter”, US Patent # 6,754,613 B2, issued 22 June 2004.

2.       A. Ivanov and A. Lowe, Time-Monitoring Appliance, U.S. Patent No. 5, 774,425, issued 30 June 1998.

3.       K. Dalmia, A. Ivanov, B. Gerson, C. Lapadat, Built-In self-test scheme for a jitter tolerance test of a clock and data recovery unit, U.S. Patent No. 5,835,501, issued 10 November 1998.

4.       A. Ivanov and Y. Wu, "Fuzzy Multiple Signature Analysis for BIST", U.S. Patent No. 5,475 694, issued 12 Dec. 1995.

White Papers

1.       C. Grecu, A.Ivanov,  P. P. Pande, A. Jantsch, E. Salminen, U. Ogras, R. Marculescu, “An Initiative toward Open Network on Chip Benchmarks”, OCP-IP website http://www.ocpip.org/socket/whitepapers/NoC-Benchmarks-WhitePaper-15.pdf , March 2007, 16 formatted pages.

EXTRA CURRICULAR

Last reviewed October 2007

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