I currently work at FPGA architecture team at AMD (former Xilinx Inc.) San Jose, CA, USA. I'm also an adjunct lecturer at Santa Clara University (teaching grad courses such as Machine Learning with FPGAs and Parallel System Architectures). At AMD, I'm Currently working on FPGA architecture, how to improve it for the next generation and optimizing applications on new architectures such as Versal.
Previously, I was a PhD Candidate in the
Department of Electrical and Computer Engineering
at the
University of British Columbia
in Vancouver, BC, Canada. During my PhD I worked at VLSI/SOC lab under supervision of Professor Guy Lemieux.
My PhD topic was:
Automated space/time scaling for streaming task graphs on reconfigurable computing platforms (FPGAs and CGRAs).
Implementing Computer Vision applications using OpenVX and developing a High Level Synthesis tool which can automatically explore space/time tradeoffs targeting different computing platforms:
1- Massively Parallel Processor Array (MPPA)
2- FPGA fabric
3- Hybrid architecture combining a Soft-Vector Processor, an ARM processor and FPGA fabric.
EDUCATION:
PhD Thesis Title: Automated Space/Time Scaling of Streaming Task Graphs on FPGAs. <pdf>
Supervisor: Professor Guy Lemieux
M.Sc. Thesis Title: FPGA placement by graph isomorphism
Supervisor: Professor Kia Bazargan
Supervisor: Professor Pejman Khadivi
email: hosseino At ece.ubc.ca
SELECTED PUBLICATIONS:
``Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs''
IEEE International Symposium On Field-Programmable Custom Computing Machines (FCCM'23)
``100% Visibility At MHz Speed: Efficient Soft Scan-Chain Insertion on AMD/Xilinx FPGAs''
International Symposium on Applied Reconfigurable Computing 2022 (ARC'22), Beijing, China
``A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs''
International Conference on Field-Programmable Logic and Applications 2020 (FPL'20),
``Low-Level Loop Analysis and Pipelining of Applications mapped to Xilinx FPGAs''
International Conference on Field-Programmable Logic and Applications 2019 (FPL'19), Barcelona, Spain
``Software-based Dynamic Overlays Require Fast, Fine-grained Partial Reconfiguration''
International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies 2019 (HEART'19), Nagasaki, Japan
``An Accelerated OpenVX Overlay for Pure Software Programmers'',
International Conference on Field-Programmable Technology 2018 (ICFPT'18), Naha, Okinawa, Japan
``JANUS: A Compilation System for Balancing Parallelism and Performance in OpenVX'',
International Conference on Machine Vision and Information Technology 2018 (CMVIT'18), Hong Kong
``Exploring Automated Space/Time Tradeoffs for OpenVX Compute Graphs'',
International Conference on Field-Programmable Technology 2017 (ICFPT'17), Melbource, Australia
``Automated Space/Time Scaling of Streaming Task Graph'',
International Workshop on Overlay Architectures for FPGAs 2016 (OLAF'16), Monterey, CA, USA
``Soft Vector Processors with Streaming Pipelines'',
International Symposium on Field-Programmable Gate Arrays 2014 (FPGA'14), Monterey, CA, USA
``FPGA Placement by Graph Isomorphism'',
International Symposium on Field-Programmable Gate Arrays 2011 (FPGA'11), Monterey, CA, USA