Ph.D. Candidate, system-on-chip research group
B.A.Sc. (T.U.I.), M.A.Sc. (UBC)
Office Location: Room 4025, 2356 Main Mall,
BC Canada V6T
My research interests are in the area of
systems-on-chip design and test, with a particular emphasis on testing
and reliability issues of their data communication infrastructures.
Recent advances in semiconductor technology raise
the challenge of
designing complex chips containing billions of transistors. In this
context, the reusability concept is an essential tool that helps coping
with this issue, where large SoCs are built using pre-existing
intellectual property (IP) cores.
Network-on-chip (NoC) interconnect infrastructures
are emerging as the
new paradigm that characterizes the on-chip data communication
architectures of gigascale SoCs.
This new design methodology can be widely adopted if
it is complemented
by efficient test mechanisms. So far the NoC test methodologies are
mainly concerned with the testing of the functional IP cores, using the
communication infrastructure as a Test Access Mechanism (TAM).
My research complements this approach by developing
the test strategy
for the interconnect infrastructure. This test strategy
minimizes the use of additional mechanisms for transporting test data
to the NoC elements under test, while allowing reduction of test time
through the use of parallel test paths and test data multicast.
Efficient test mechanisms may not be sufficient for
guaranteeing good yield for large production volume MP-SoCs.
Fault tolerance must be an integral component when designing large,
complex chips. I am looking at ways to integrate fault tolerance
mechanisms at all levels in the MP-SoCs communication/application stack.
I am also interested and actively
development of benchmarks and benchmark circuits for networks on chip.
This ongoing work takes place within the Network-on-chip Benchmarking
Workgroup at OCP-IP (www.ocpip.org/wiki/university)
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