Eddie Hung

PhD Candidate with the System-on-Chip research group,
in the Electrical and Computer Engineering Department
at The University of British Columbia

I am currently working on enhancing the debug-ability of circuits implemented on FPGAs.

Our speculative debug insertion tool, In-Spec, is available for download here.

Our delay model from "A Detailed Delay Path Model for FPGAs" is available for download here.

Doxygen-generated documentation of:

• VPR 6.0 -- [Part of The Verilog-to-Routing (VTR) Project http://code.google.com/p/vtr-verilog-to-routing/]
• VPR 5.0 -- [http://www.eecg.utoronto.ca/vpr/]
• ABC -- [http://www.eecs.berkeley.edu/~alanmi/abc/]
• VIS/GLU -- [http://vlsi.colorado.edu/~vis/]
• ODIN-II -- [http://code.google.com/p/odin-ii]

Google Profile