Ed Casas (firstname.lastname@example.org) Sun, 7 Mar 1999 08:15:16 -0800
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Date: Sun, 7 Mar 1999 08:15:16 -0800 From: Ed Casas <firstname.lastname@example.org> Subject: Re: Reset?
> I have a few questions: > > 1) is reset asynchronous or synchronous (ie. should i have a > fetch, execute, and reset state or is reset just treated as the > other function calls) Reset, like everything else in your design, should be synchronous. The controller state will change state to the fetch state will on any rising edge of the clock where the reset signal is asserted. The PC will also change `state' to "00000" on the rising edge of the clock if reset is asserted. > 2) my implementation of the main entity only has component > instantiations and no sequential statements, is this okay? Yes, this is fine. In this course we only use sequential statements to model registers and you should not need to instantiate any registers in the top level of your design. However, due to an oversight when writing up the assignment, you will also need to include a multiplexer (conditional assignment) in the top level of your design in addition to component instantiations. This mux selects one of the two address sources to be supplied to the memory address input. It would look something like: mem_addr_in <= pc_addr_out when fetch = '1' else instr_reg_out(4 downto 0) ; -- Ed Casas email@example.com http://casas.ece.ubc.ca +1 604 822-2592