Dipanjan Sengupta

I am a PhD candidate in the System on Chip Laboratory, Department of Electrical and Computer Engineering at University of British Columbia, where I am advised by Dr. Resve Saleh and Dr.Steve Wilton. I received a BS in Computer Science from University of Calcutta in 2000, Bachelor of Technology from Institute of RadioPhysics and Electronics in 2003 and MS in Electrical and Computer Engineering from UBC in 2005.

I am interested in low power System-on-Chip design techniques. During my masters studies at The University of British Columbia I have investigated the effect of supply and threshold voltage scaling on power and delay and then identified feasible region of operation in the supply vs. threshold plane. A fundamental relationship was established between the optimal operating points and the generalized design metrics. The focus of my research during PhD is voltage island design and power gating technique in a System-on-Chip. The methodology to choose the best set of supply voltages, use multi-threshold design techniques based on Power State Machine and use mixed deterministic-heuristic voltage assignment technique to reduce chip-level power, area and design time is the key goal of research. In the future I would like to extend my knowledge in power aware design techniques to heterogeneous multi-core System-on-Chip.

You can find my CV here and resume here.

• D. Sengupta and R. Saleh, “Generalized Power-Delay Metrics in Deep Submicron CMOS Designs”, IEEE Transactions on Computer Aided Design, Vol. 26, Issue 1, Jan. 2007, pp. 183-189.

• D. Sengupta and R. Saleh, “Application-Driven Voltage Island Partitioning for Low-power System-on-Chip Design”, IEEE Transactions on Computer Aided Design, Vol. 28, Issue 3, March 2009, pp. 316-326.

• C. Grecu, D. Sengupta, P.P. Pande, A. Ivanov, R. Saleh, "Self-Repairable SoC Communication Links using Crosspoint Redundancy", submitted, IEEE Transactions on VLSI (submitted February 2008).

• D. Sengupta and R. Saleh, “Power-Delay Metrics Revisited for 90nm CMOS Technology”, IEEE International Symposium on Quality of Electronic Design (ISQED), March 21-23 2005, pp. 291-296.

• D. Sengupta and R. Saleh, “Constraint-based Voltage Island Partitioning”, IEEE Midwest Symposium on Circuits and Systems (MWSCAS/NEWCAS), August 5-7 2007, pp. 1050-1053.

• D. Sengupta and R. Saleh, “Application-driven Floorplan-aware Voltage Island Design”, IEEE Design Automation Conference (DAC), June 8-13, 2008, pp. 155-160.

• D. Sengupta and R. Saleh, “Supply Voltage Selection in Voltage Island based SoC Design”, IEEE International SOC Conference (SOCC), September 17-20, 2008, pp. 219-222.

• D. Sengupta MS Thesis, “Application of Generalized Power-Delay Metrics to Supply and Threshold Selection in Deep Submicron CMOS”, August 2005

• Investigate supply and threshold voltage variation and their effects on design parameters using HSpice, Synopsys and Cadence tools.

• Formulate methodology of supply and threshold voltage selection.

• Investigate Voltage Island design techniques

• Digital Integrated Circuits : ECE 481 ( Spring 2009)

• Digital Systems Design : ECE 353 ( Summer 2009 )

• Technology and Society : APSC 261 ( Winter 2009 )

TEACHING ASSISTANT

• Introduction to Microcomputers (ECE 259)
• Digital Systems Design (ECE 353)
• Electronic Circuits I (ECE 254)
• Project Integrated Program (ECE PiP)

• Ph.D. Candidate (Electrical and Computer Engineering) August 2009 (expected)
  University of British Columbia, Canada
  Advisor: Dr. Resve Saleh and Dr. Steve Wilton
  Thesis: Power Reduction in an SoC using Voltage Island and Power Gating Techniques.
• M.A.Sc. (Electrical and Computer Engineering) August 2005
  University of British Columbia, Canada
  Advisor: Dr. Resve Saleh
• Bachelor of Technology July 2003
  Institute of RadioPhysics and Electronics, University of Calcutta, India
  Advisor: Dr. Susanta Sen
• Bachelor of Science July 2000
  University of Calcutta, India

• ECE-479: Introduction to VLSI Systems
• ECE-481: Deep Submicron Digital Integrated Circuit Design
• ECE-578: Integrated Circuit Design and Test
• ECE-579: Advanced Topics in VLSI Design
• ECE-583: CAD Algorithms for Integrated Circuits
• ECE-595: Computer Architecture for Parallel Processing
• ECE-538A: Asynchronous Design
• ECE-576: Semiconductor Theory for Device Applications

• National Scholarship Award, Government of India, 2000
• M.A.Sc Tuition Scholarship, UBC, 2003
• PhD Tuition Scholarship, UBC, 2005

• Journal reviewer: IEEE Transactions on Computer Aided Design
• Conference reviewer: MWSCAS, ISCAS