This page contains the code files and the spreadsheets for the works related to analytical modeling.

• Spreadsheet for area, depth and wirelength model:
  [version: Microsoft Excel 97/2000/XP]
  
  Click here to download the spreadsheet with model equations for area, depth and wirelength of an FPGA architecture.
  The spreadsheet also contains the values of the Rent parameter, the number of 2-input lookup tables (LUT) and the maximul post-techmapping depth for 20 large MCNC bechmark circuits. Consult the notes on the spreadsheet for details on using the spreadsheet.
  
  [Note: This spreadsheet uses a macro to calculate a function φ(p,f_max), where φ(p,f_max) is defined by Equation (10) of the publication of Lam et al[1]. This function is eventually used to calculate the fan-out of a circuit.]
  
  
  
  
• Spreadsheet for area, depth and wirelength model: (without macro)
  [version: Microsoft Excel 97/2000/XP]
  
  Click here to download the spreadsheet without the macro. You will still need to enter the value of φ(p,f_max) manually. Alternatively, you may incorporate the macro from here. Consult the spreadsheet for details.
  
  
  
  
• Spreadsheet for area, depth and wirelength model:
  [version: OpenOffice]
  
  Click here to download the spreadsheet in OpenOffice format. This spreadsheet also contains the macro to calculate the function φ(p,f_max).
  
  
  
  
• C-Code for collecting model results by sweeping architectural parameters
  
  
  Click here to download the archieved file. Please read the README file first.
  
  
  
  
• Scripts to generate and analyze crossbar switches with varying workloads
  
  
  Click here to download the archieved file. Please read the README file first.

The spreadsheets use the models from the following publications:

[1] Andrew Lam, Steven J.E. Wilton, Philip Leong, Wayne Luk. "An Analytical Model Describing the Relationship between Logic Architecture and FPGA Density". FPL 2008. August, 2008. [abstract] [pdf]

[2] Joydip Das, Steven J.E. Wilton, Philip Leong, Wayne Luk. "Modeling Post-Techmapping and Post-Clustering FPGA Circuit Depth".FPL 2009. Prague, Czech Republic, Aug. 31-Sep. 2, 2009 [abstract] [pdf]

[3] Alastair M. Smith, Joydip Das, Steven J.E. Wilton. "Wirlength Modeling for Homogeneous and Heterogeneous FPGA Architecture Development". FPGA 2009. Monterey, California, February 22-24, 2009 [abstract] [pdf]

[4] Wei M. Fang, Jonathan Rose. "Modeling Routing Demand for Early-Stage FPGA Architecture Development". FPGA 2008. Monterey, California, February 24-26, 2008 [ACM Link]

[5] Joydip Das, Andrew Lam, Steven J.E. Wilton, Philip Leong, Wayne Luk. "An Analytical Model Relating FPGA Architecture to Logic Density and Depth". Accepted for Publication in IEEE T-VLSI [abstract]

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[Page last updated on August 22, 2010]