Anthony J. Yu
Hello
and welcome. My name is Anthony Yu and I was a graduate student in the Department
of Electrical and Computer Engineering at The
University of British Columbia. I worked in the System-on-a-Chip research
group under the supervision of professor Guy
Lemieux. Together, we explored the factors that affected FPGA yield,
investigated methods of enhancing FPGA yield through the application of
defect-tolerant techniques, and analyzed the tradeoffs between yield and
redundancy.
About Me
I am currently working at Intel Corporation. My primary role there is to enhance the development of Intel products through the use of FPGAs. Prior to this, I have worked at Agilent Technologies designing network test equipment, and at Zeugma Systems developing high-speed packet processors.
In my down time, I am an avid traveler, photographer and food fiend. These are my passions in life; I strive to do all three whenever time permits. So far, I’ve had the opportunity to eat my way across Europe, Asia and North America - 100+ cities in over 20 different countries. In the future, I hope to add to those numbers by climbing Machu Picchu, going on a photographic safari in Africa and visiting the Galapagos Islands.
If you want to further discuss my work at UBC and or my current or past work experiences, please feel free to send me an email.
Contact Information
Mailing Address: ATTN: Anthony J. Yu
Electrical and Computer Engineering
The University of British Columbia
5500 - 2332 Main Mall
Vancouver, BC, V6T 1Z4
Canada
Email: anthony (dot) yj (dot) yu (at) gmail (dot) com
Publications
· A. Yu, ``Defect tolerance for yield enhancement of FPGA interconnect using fine-grain and coarse-grain redundancy'', Master’s thesis, Dept. of Electrical and Computer Engineering, Univ. of British Columbia, August 2005. [abstract] [ppt]
· A. Yu, G. Lemieux, ``FPGA Defect Tolerance: Impact of Granularity'', Int'l Conference on Field-Programmable Technology, Singapore, pp. 189 - 196, December 2005. [abstract] [ppt]
· A. Yu, G. Lemieux, ``Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement'', Int'l Conference on Field-Programmable Logic and Applications, Tampere, Finland, pp. 255 - 262, August 2005. [abstract] [ppt]
· G. Lemieux, E. Lee, M. Tom, and A. Yu, ``Directional and Single-Driver Wires in FPGA Interconnect'', IEEE International Conference on Field-Programmable Technology, Brisbane, Australia, pp. 41 - 48, December 2004. - Best Paper Award. [abstract]
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