Tutorial on GPGPU-Sim: A Performance Simulator for Massively Multithreaded Processor Research

Tutorial Slides

Held in conjunction with The 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42)
Westin New York at Times Square, New York City, Morning, Sunday 13 December, 2009

Abstract

This tutorial will present the simulation infrastructure and related tools for the GPGPU-Sim simulator. GPGPU-Sim is a detailed simulator that models a modern GPU running applications written in CUDA and OpenCL (without requiring any source code modifications). CUDA and OpenCL are extensions of the familar C programming language used for programming GPUs and related many-core architectures. The rapidly growing number of applications written for these devices typically contain tens of thousands of threads making them an interesting workload for future many-core architecture research. The simulator can be downloaded from the GPGPU-Sim Google-groups page. Over 200 users have signed up to use GPGPU-Sim since it was made available earlier this year. The focus of this tutorial is on learning what one needs to know to quickly begin using the simulator for research.

Schedule

Start 8:30 am
Break 10-10:30 am
Finish 12:00 pm

Registration

To register click here. For more details on MICRO-42, go here.

Organizers

Tor M. Aamodt, Ali Bakhoda, Wilson Fung (The University of British Columbia)

Topics covered

1. Brief Review of GPU Programming Models (30 minutes)
2.GPGPU-Sim Overview (30 minutes)
3.GPGPU-Sim Internals
(a) Microarchitecture model (30 minutes)
(b) Software organization and hacking tips (30 minutes)
(c) Example modifications (30 minutes)
4.GPGPU-Sim Tools (30 minutes)

Bibliography

[1] Ali Bakhoda, George Yuan, Wilson W. L. Fung, Henry Wong, Tor M. Aamodt, Analyzing CUDA Workloads Using a Detailed GPU Simulator, In proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 163-174, Boston, MA, April 26-28, 2009.

[2] Wilson W. L. Fung, Ivan Sham, George Yuan, and Tor M. Aamodt, Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow, In proceedings of the 40th IEEE/ACM International Symposium on Microarchitecture (MICRO-40), pp. 407-418, Chicago, IL, December 1-5, 2007.

[3] George L. Yuan, Ali Bakhoda, Tor M. Aamodt, Complexity Effective Memory Access Scheduling for Many-Core Accelerator Architectures, To appear in: 42nd IEEE/ACM International Symposium on Microarchitecture (MICRO-42), New York, NY, December 12-16, 2009.

[4] Aaron Ariel, Wilson W. L. Fung, Andrew Turner, Tor M. Aamodt, Visualizing Complex Dynamics in Many-Core Accelerator Architectures, To appear in: Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), White Plains, NY, March 28-30, 2010.