On fault coverage in VLSI built-in self-test with multiple intermediate signature analysis

TitleOn fault coverage in VLSI built-in self-test with multiple intermediate signature analysis
Publication TypeConference Paper
Year of Publication1993
AuthorsZhang, C., Y. Wu, and A. Ivanov
Conference NameElectrical and Computer Engineering, 1993. Canadian Conference on
Pagination449 -452 vol.1
Date Publishedsep.
Keywordsbenchmark circuits, built-in self test, fault coverage, fault coverage models, fault coverage performance, integrated circuit testing, logic testing, multiple intermediate signature analysis, signatures check times, VLSI, VLSI built-in self-test
Abstract

This paper studies the fault coverage performance with multiple intermediate signature analysis. Two fault coverage models are presented. Unlike the results reported in the literature, these models reveal that the fault coverage with multiple intermediate signature analysis depends on the times when the signatures are checked. Experimental results on benchmark circuits are reported

URLhttp://dx.doi.org/10.1109/CCECE.1993.332197
DOI10.1109/CCECE.1993.332197

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