Electrical and Computer Engineering
2332 Main Mall
Vancouver,
BC
Canada
V6T 1Z4
Tel +1.604.822.2872
Fax +1.604.822.5949
Email:
info@ece.ubc.ca
| Title | On fault coverage in VLSI built-in self-test with multiple intermediate signature analysis |
| Publication Type | Conference Paper |
| Year of Publication | 1993 |
| Authors | Zhang, C., Y. Wu, and A. Ivanov |
| Conference Name | Electrical and Computer Engineering, 1993. Canadian Conference on |
| Pagination | 449 -452 vol.1 |
| Date Published | sep. |
| Keywords | benchmark circuits, built-in self test, fault coverage, fault coverage models, fault coverage performance, integrated circuit testing, logic testing, multiple intermediate signature analysis, signatures check times, VLSI, VLSI built-in self-test |
| Abstract | This paper studies the fault coverage performance with multiple intermediate signature analysis. Two fault coverage models are presented. Unlike the results reported in the literature, these models reveal that the fault coverage with multiple intermediate signature analysis depends on the times when the signatures are checked. Experimental results on benchmark circuits are reported |
| URL | http://dx.doi.org/10.1109/CCECE.1993.332197 |
| DOI | 10.1109/CCECE.1993.332197 |