The Coarse-Grained / Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units

TitleThe Coarse-Grained / Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units
Publication TypeConference Paper
Year of Publication2008
AuthorsYul, C. W., J. Lamoureux, S. J. E. Wilton, P. H. W. Leong, and W. Luk
Conference NameProgrammable Logic, 2008 4th Southern Conference on
Pagination63 -68
Date Publishedmar.
Keywordscoarse-grained programmable logic, embedded floating-point arithmetic units, embedded systems, empirical study, field programmable gate arrays, fine-grained logic interface, floating point arithmetic, FPGA, interconnections, interconnects, logic design, network routing, pin arrangement, routing architecture
Abstract

This paper examines the interface between fine-grained and coarse-grained programmable logic in FPGAs. Specifically, it presents an empirical study that covers the location, pin arrangement, and interconnect between embedded floating point units (FPUs) and the fine-grained logic fabric in FPGAs. The results show that (1) FPUs should be square, (2) FPUs should be positioned tightly near the center of the FPGA and (3) that the FPU pins should be arranged on four sides of the FPU.

URLhttp://dx.doi.org/10.1109/SPL.2008.4547733
DOI10.1109/SPL.2008.4547733

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