Vector Processing as a Soft-core CPU Accelerator

TitleVector Processing as a Soft-core CPU Accelerator
Publication TypeJournal Article
Year of Publication2008
AuthorsYu, J., G. Lemieux, and C. Eagleston
JournalFPGA 2008: 16th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
Pagination222–231
Abstract

The currently accepted method of accelerating applications in FPGA soft processor systems is to design a custom hardware accelerator. This paper suggests the alternative approach of adding a vector processing core to the soft processor as a general-purpose accelerator. The approach has the benefit of a purely software-oriented development model. With no hardware design experience needed, a software programmer can make area-versus-performance tradeoffs by scaling the number of functional units or vector lanes. This paper shows that a vector processing architecture maps efficiently into an FPGA and provides a scalable amount of performance for a reasonable amount of area. Three configurations of the soft vector processor with different performance levels are estimated to achieve scalable speedup ranging from 3-29x for 6-30x the area of a Nios II/s processor on three benchmark kernels. The results compare favourably to accelerators designed using Altera's C2H compiler, a C-to-hardware tool that is also easy to use.

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