A Case for Soft Vector Processors in FPGAs

TitleA Case for Soft Vector Processors in FPGAs
Publication TypeConference Paper
Year of Publication2007
AuthorsYu, J., and G. Lemieux
Conference NameField-Programmable Technology, 2007. ICFPT 2007. International Conference on
Pagination341 -344
Date Publisheddec.
Keywordsfield programmable gate arrays, FPGA, hardware accelerators, hardware design knowledge, logic design, microprocessor chips, Nios II processor, soft vector processors, software developers, Stratix III, vector processing, vector processor systems, vector programming model
Abstract

Embedded applications today require high computational power that is not met by current FPGA-based soft processors. Although performance of data-parallel applications can be addressed by custom-designed hardware accelerators, such an approach is difficult for embedded software developers with little hardware design experience. Instead, vector processing can be used to speed up these same data-parallel applications. The vector programming model is easy to understand by software developers, making it easier for them to extract the parallelism without any hardware design knowledge. This paper proposes a soft vector processor for the Stratix III FPGA that can be scaled to different levels of performance and resource utilization. It has several configurable features that can be included or excluded to optimize the soft processor for a given application. Performance estimates of the soft vector processor using three embedded benchmark kernels show speedup of up to 16.6 x over an idealized Nios II processor while using 10.9 x the area.

URLhttp://dx.doi.org/10.1109/FPT.2007.4439281
DOI10.1109/FPT.2007.4439281

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