FPGA defect tolerance: impact of granularity

TitleFPGA defect tolerance: impact of granularity
Publication TypeConference Paper
Year of Publication2005
AuthorsYu, A. J., and G. Lemieux
Conference NameField-Programmable Technology, 2005. Proceedings. 2005 IEEE International Conference on
Pagination189 -196
Date Publisheddec.
Keywordscoarse-grain redundancy, fault tolerance, field programmable gate arrays, fine-grain redundancy, FPGA architecture, FPGA defect tolerance, integrated circuit reliability, logic design, nanotechnology, redundancy
Abstract

As device sizes shrink, FPGAs are increasingly prone to manufacturing defects. The ability to tolerate multiple defects is anticipated to be very important at 45nm and beyond. One possible approach to this growing problem is to add redundancy to create a defect-tolerant FPGA architecture. Using area, delay and yield metrics, this paper compares two redundancy strategies: a coarse-grain approach using spare rows and columns and a fine-grain approach using spare wires. For low defect levels and large array sizes, the coarse-grain approach offers a lower area overhead, but it is relatively intolerant to an increase in defect count. In contrast, the fine-grain approach has a fixed overhead of up to 50%, but the architecture can tolerate an increasing number of defects as array size grows. To achieve a similar level of yield recovery, the coarse-grain approach requires an area overhead in excess of 100%

URLhttp://dx.doi.org/10.1109/FPT.2005.1568545
DOI10.1109/FPT.2005.1568545

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