Congestion Estimation and Localization in FPGAs: A Visual Tool for Interconnect Prediction

TitleCongestion Estimation and Localization in FPGAs: A Visual Tool for Interconnect Prediction
Publication TypeJournal Article
Year of Publication2007
AuthorsYeager, D., D. Chiu, and G. Lemieux
JournalProceedings of SLIP '07: 2007 International Workshop on System Level Interconnect Prediction
Pagination33–40
Abstract

In this paper, we are concerned with locating the most congested regions in FPGA designs before routing is completed. As well, we are interested in the amount of congestion in these locations relative to surrounding areas. If this estimation is done accurately and early enough, e.g. prior to routing or even prior to placement, the data can be used during clustering, placement and perhaps during routing to avoid or spread out congestion before it becomes a problem. We implemented several estimation methods in the VPR tool set and visually compare estimation results to an actual routing congestion map. We find that standard image processing techniques such as blending and peak saturation considerably improve the quality of estimation for all metrics.

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