Open defects detection within 6T SRAM cells using a No Write Recovery Test Mode

TitleOpen defects detection within 6T SRAM cells using a No Write Recovery Test Mode
Publication TypeConference Paper
Year of Publication2004
AuthorsYang, J., B. Wang, and A. Ivanov
Conference NameVLSI Design, 2004. Proceedings. 17th International Conference on
Pagination493 - 498
Keywordsdata retention faults, design for test technique, design for testability, DFT technique, fault free memory cells, fault simulation, faulty memory cells, high speed SRAM version, integrated circuit testing, march tests, no write recovery test mode, open defects detection, SRAM cells, SRAM chips, static random access memory cells, test cycles, test time requirements, undetectable defects
Abstract

The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) technique that we refer to as No Write Recovery Test Mode (NWRTM) to detect all open defects, some of which produce Data Retention Faults (DRFs) but are undetectable by typical March tests. We demonstrate the effectiveness of our proposed technique by only applying it to fault-free memory cells and faulty cells with those undetectable defects but all the open defects are covered since our DFT technique is implemented by simply adding extra test cycles into typical March tests. Two 6T SRAM cell models, one a high-speed version and the other a low-power one, representing extreme cases according to traditional design methodologies, were designed to validate our proposed NWRTM at the circuit level. Simulation results show that our NWRTM amounts to a shorter total test time and improved open defect detection capability. In addition, in comparison to other DFT techniques, NWRTM requires the least additional design effort, and imply less area and no performance penalties.

URLhttp://dx.doi.org/10.1109/ICVD.2004.1260969
DOI10.1109/ICVD.2004.1260969

a place of mind, The University of British Columbia

Electrical and Computer Engineering
2332 Main Mall
Vancouver, BC Canada V6T 1Z4
Tel +1.604.822.2872
Fax +1.604.822.5949
Email:

Emergency Procedures | Accessibility | Contact UBC | © Copyright 2020 The University of British Columbia