Product-term-based synthesizable embedded programmable logic cores

TitleProduct-term-based synthesizable embedded programmable logic cores
Publication TypeJournal Article
Year of Publication2006
AuthorsYan, A., and S. J. E. Wilton
JournalVery Large Scale Integration (VLSI) Systems, IEEE Transactions on
Volume14
Pagination474 - 488
Date Publishedmay.
ISSN1063-8210
Keywordsbenchmark circuits, circuit layout, embedded programmable logic cores, embedded systems, field programmable gate arrays, flip-flops, product term arrays, proof-of-concept layout, sequential logic, stand-alone programmable cores, synthesizable logic cores
Abstract

As integrated circuits become increasingly complex, the ability to make post-fabrication changes will become more important and attractive. This capability can be realized by using programmable logic cores. Currently, such cores are available from vendors in the form of "hard" macro layouts. Previous work has suggested an alternative approach: vendors supply a synthesizable version of their programmable logic core and the integrated circuit designer synthesizes the programmable logic fabric using standard cells. Although this technique suffers increased delay, area, and power, the task of integrating such cores is far easier than the task of integrating "hard" cores into an ASIC or system-on-chip (SoC). When implementing a small amount of logic, this ease of use may be more important than the increased overhead. This paper presents a new family of architectures for these "synthesizable" cores; unlike previous architectures, which were based on lookup-tables (LUTs), the new family of architectures is based on a collection of product-term arrays. Compared to LUT-based architectures, the new architectures result in density improvements of 35% and speed improvements of 72% on standard benchmark circuits. The improvement is due to the inherent efficiency of product-term-based designs for small logic circuits. In addition, we describe novel ways of enhancing synthesizable architectures to support sequential logic. We show that directly embedding flip-flops as is done in stand-alone programmable cores will not suffice. Consequently, we present two novel architectures employing our solution and optimize and compare them. Finally, we describe a proof-of-concept layout employing one of our proposed architectures.

URLhttp://dx.doi.org/10.1109/TVLSI.2006.876097
DOI10.1109/TVLSI.2006.876097

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