Sequential synthesizable embedded programmable logic cores for system-on-chip

TitleSequential synthesizable embedded programmable logic cores for system-on-chip
Publication TypeConference Paper
Year of Publication2004
AuthorsYan, A., and S. J. E. Wilton
Conference NameCustom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004
Pagination435 - 438
Date Publishedoct.
Keywordscircuit optimisation, circuitry architectures, combinational architectures, embedded systems, integrated circuit design, integrated circuit testing, logic design, post-fabrication integrated circuit flexibility, programmable logic devices, proof-of-concept chip, sequential circuits, sequential logic, sequential synthesizable embedded programmable logic cores, soft synthesizable programmable logic cores, system-on-chip

Previous work has suggested that "soft" synthesizable programmable logic cores can efficiently provide small amounts of post-fabrication flexibility to integrated circuits. Previous architectures restrict the circuitry assigned to the core to be combinational. We present two methods to enhance these architectures to support sequential logic. We apply these methods to a previously developed fabric, and optimize and compare them. We also describe a proof-of-concept chip employing one of our techniques.


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