SoC implementation issues for synthesizable embedded programmable logic cores

TitleSoC implementation issues for synthesizable embedded programmable logic cores
Publication TypeConference Paper
Year of Publication2003
AuthorsWu, J. C. H., V. Aken'Ova, S. J. E. Wilton, and R. Saleh
Conference NameCustom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003
Pagination45 - 48
Date Publishedsep.
Keywordsarea overhead, clock tree synthesis, core connection, core size choice, delay overhead, embedded programmable logic cores, hard cores, logic design, programmable logic devices, SoC implementation issues, soft cores, standard library cells, synthesizable logic cores, system-on-chip

As integrated circuits have become more and more complex, the ability to make post-fabrication changes will become more and more attractive. This ability can be realized using programmable logic cores. Currently, such cores are available from vendors in the form of a "hard" layout. An alternative approach is to use a "soft", or synthesizable programmable logic core that can be synthesized using standard library cells. In this paper, we describe the design of an integrated circuit that incorporates such a synthesizable programmable logic core. We focus on implementation issues that arose; specifically, the choice of core size, the connection of the core to the rest of the integrated circuit, and clock tree synthesis. We also present area and delay overhead results.


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