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| Title | Minimal hardware multiple signature analysis for BIST |
| Publication Type | Conference Paper |
| Year of Publication | 1993 |
| Authors | Wu, Y., and A. Ivanov |
| Conference Name | VLSI Test Symposium, 1993. Digest of Paper s., Eleventh Annual 1993 IEEE |
| Pagination | 17 -20 |
| Date Published | apr. |
| Keywords | aliasing, BIST multiple intermediate signature analysis, built-in self test, fault-free output sequence, Integrated logic circuits, logic testing, nonrecurring CPU time expenditure, recurring silicon area savings |
| Abstract | Proposes a new BIST multiple intermediate signature analysis scheme which checks n signatures against a single reference. Therefore, the circuitry for checking n signatures is essentially the same as that for checking one signature. The scheme is based on a manipulation of the CUT's fault-free output sequence. No circuit modification is required. The cost for implementing the scheme is a small nonrecurring CPU time expenditure in the design phase. In return, the scheme yields significant recurring silicon area savings, and reduced aliasing |
| URL | http://dx.doi.org/10.1109/VTEST.1993.313314 |
| DOI | 10.1109/VTEST.1993.313314 |