Accelerated path delay fault simulation

TitleAccelerated path delay fault simulation
Publication TypeConference Paper
Year of Publication1992
AuthorsWu, Y., and A. Ivanov
Conference NameVLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Paper s., 1992 IEEE
Pagination1 -6
Date Publishedapr.
Keywordsbacktrace process, circuit nodes, CPU time, digital simulation, fanout, fault location, ISCAS'85 benchmark circuits, logic CAD, logic gates, memory efficiency, parallel pattern, path delay fault simulation, speed efficiency, subpath event sensitizability, subpath event sensitizability robustness
Abstract

Due to fanout in a circuit, the speed efficiency of existing path delay fault simulation algorithms suffers from redundant evaluations of many circuit nodes in the backtrace process of every simulation pass. This paper introduces two new concepts-subpath event sensitizability (SES) and subpath event sensitizability robustness (SESR). Based on these new concepts, the authors propose a new procedure for path delay fault simulation whereby each node of the simulated circuit is evaluated only once per simulation pass in the backtrace process. Experiments with the ISCAS'85 benchmark circuits show that the procedure accelerates path delay fault simulation significantly. The proposed procedure can be implemented for parallel pattern path delay fault simulation. The concepts of SES and SESR can also improve both CPU time and memory efficiency of path delay fault simulation if only a subset of all the paths is considered

URLhttp://dx.doi.org/10.1109/VTEST.1992.232715
DOI10.1109/VTEST.1992.232715

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