Placement and routing for non-rectangular embedded programmable logic cores in SoC design

TitlePlacement and routing for non-rectangular embedded programmable logic cores in SoC design
Publication TypeConference Paper
Year of Publication2004
AuthorsWong, T., and S. J. E. Wilton
Conference NameField-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on
Pagination65 - 72
Date Publisheddec.
Keywordscritical path improvement, embedded systems, field programmable gate arrays, I/O constraints, integrated circuit layout, IP cores, logic design, nonrectangular embedded programmable logic cores, O-shaped cores, placement algorithms, rectangular FPGA, routing algorithms, SoC design, square FPGA, stand-alone FPGA, system-on-chip, U-shaped cores, user circuits
Abstract

As SoC design enters into mainstream usage, the ability to make post-fabrication changes will become more and more attractive. This ability can be realized using programmable logic cores. These cores are like any other IP in the SoC design methodology, except that their function can be changed after fabrication. In many cases, non-rectangular programmable logic cores are required, either to better mesh with the other IP cores, or because of I/O constraints. In order to use programmable logic cores, placement and routing algorithms are required to implement user circuits on the core. Existing placement and routing algorithms that target programmable logic were optimized for stand-alone FPGAs which are invariably square or rectangular. We show that these algorithms do not work well when targetting non-rectangular programmable logic cores, and we present enhancements to existing placement and routing algorithms that allow the algorithms to better target these cores. It is shown that the new algorithms lead to a 12% critical path improvement for "U"-shaped cores, and a 4% improvement for "O"-shaped cores. The density and speed penalty for using these non-rectangular cores is significant, compared to square cores, however, we show that the penalty would be significantly larger if the original algorithms were used.

URLhttp://dx.doi.org/10.1109/FPT.2004.1393252
DOI10.1109/FPT.2004.1393252

a place of mind, The University of British Columbia

Electrical and Computer Engineering
2332 Main Mall
Vancouver, BC Canada V6T 1Z4
Tel +1.604.822.2872
Fax +1.604.822.5949
Email:

Emergency Procedures | Accessibility | Contact UBC | © Copyright 2020 The University of British Columbia