Design considerations for soft embedded programmable logic cores

TitleDesign considerations for soft embedded programmable logic cores
Publication TypeJournal Article
Year of Publication2005
AuthorsWilton, S. J. E., N. Kafafi, J. C. H. Wu, K. A. Bozman, V. O. Aken'Ova, and R. Saleh
JournalSolid-State Circuits, IEEE Journal of
Volume40
Pagination485 - 497
Date Publishedfeb.
ISSN0018-9200
KeywordsASIC, design considerations, field programmable gate arrays, field-programmable gate arrays, fine-grain programmability, hard programmable logic core, hard rectangular layouts, integrated circuit design, nonrectangular architecture, post-fabrication changes, power overhead, proof-of-concept integrated circuit, SoC design, soft embedded programmable logic cores, soft programmable logic core architectures, standard cells, synthesized RTL, system-on-chip
Abstract

As integrated circuits become increasingly more complex and expensive, the ability to make post-fabrication changes will become much more attractive. This ability can be realized using programmable logic cores. Currently, such cores are available from vendors in the form of "hard" rectangular layouts. We focus on an alternative approach for fine-grain programmability: vendors supply a synthesized RTL version of their programmable logic core (a "soft" core) and the integrated circuit designer synthesizes the programmable logic fabric using standard cells. Although this technique suffers in terms of speed, density, and power overhead, the task of integrating such cores is far easier than the task of integrating "hard" cores into an ASIC or SoC. When the required amount of programmable logic is small, this ease of use may be more important than the increased overhead. This paper presents two synthesized "soft" programmable logic core architectures and describes their associated place and route issues. We compare the two architectures to each other, and to a "hard" programmable logic core. We also show how these cores can be made more efficient by creating a nonrectangular architecture, an option not usually available to "hard" core vendors. Finally, a proof-of-concept integrated circuit containing one of these cores is described.

URLhttp://dx.doi.org/10.1109/JSSC.2004.841038
DOI10.1109/JSSC.2004.841038

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