Title | The impact of pipelining on energy per operation in field-programmable gate arrays |
Publication Type | Journal Article |
Year of Publication | 2004 |
Authors | Wilton, S. J. E., S. S. Ang, and W. Luk |
Secondary Authors | Becker, J., M. Platzner, and S. Vernalde |
Journal | Field-Programmable Logic and Applications, Proceedings |
Volume | 3203 |
Pagination | 719–728 |
ISSN | 0302-9743 |
Abstract | This paper investigates experimentally the quantitative impact of pipelining on energy per operation for two representative FPGA devices: a 0.13 mum CMOS high density/high speed FPGA (Altera Stratix EP1S40), and a 0.18 mum CMOS low-cost FPGA (Xilinx XC2S200). The results are obtained by both measurements and execution of vendor-supplied tools for power estimation. It is found that pipelining can reduce the amount of energy per operation by between 40% and 90%. Further reduction in energy consumption can be achieved by power-aware clustering, although the effect becomes less pronounced for circuits with a large number of pipeline stages. |