The impact of pipelining on energy per operation in field-programmable gate arrays

TitleThe impact of pipelining on energy per operation in field-programmable gate arrays
Publication TypeJournal Article
Year of Publication2004
AuthorsWilton, S. J. E., S. S. Ang, and W. Luk
Secondary AuthorsBecker, J., M. Platzner, and S. Vernalde
JournalField-Programmable Logic and Applications, Proceedings
Volume3203
Pagination719–728
ISSN0302-9743
Abstract

This paper investigates experimentally the quantitative impact of pipelining on energy per operation for two representative FPGA devices: a 0.13 mum CMOS high density/high speed FPGA (Altera Stratix EP1S40), and a 0.18 mum CMOS low-cost FPGA (Xilinx XC2S200). The results are obtained by both measurements and execution of vendor-supplied tools for power estimation. It is found that pipelining can reduce the amount of energy per operation by between 40% and 90%. Further reduction in energy consumption can be achieved by power-aware clustering, although the effect becomes less pronounced for circuits with a large number of pipeline stages.

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