Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays

TitleInterconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays
Publication TypeConference Paper
Year of Publication2004
AuthorsWilton, S. J. E., N. Kafafi, B. Mei, and S. Vernalde
Conference NameField-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on
Pagination33 - 40
Date Publisheddec.
Keywordscompiler, configuration bit storage area, field programmable gate arrays, fully-connected network, instruction throughput, integrated circuit design, integrated circuit interconnections, interconnect architectures, loop-level parallelism, loop-level pipelined schedules, modulo-scheduled coarse-grained reconfigurable arrays, pipeline processing, point-to-point interconnect architecture, program compilers, reconfigurable architectures, reconfigurable system
Abstract

The ability of a compiler to exploit loop-level parallelism in a reconfigurable array is significantly affected by the amount of flexibility in the interconnect architecture. A less flexible interconnect will make it more difficult for the compiler to find efficient loop-level pipelined schedules, leading to reduced instruction throughput, and larger configuration bit storage area. In this paper, we determine the optimum flexibility and topology for a point-to-point interconnect architecture in a reconfigurable system. We present four topologies, and show that their performance per unit area is significantly better than that that would be obtained if a fully-connected network had been used.

URLhttp://dx.doi.org/10.1109/FPT.2004.1393248
DOI10.1109/FPT.2004.1393248

a place of mind, The University of British Columbia

Electrical and Computer Engineering
2332 Main Mall
Vancouver, BC Canada V6T 1Z4
Tel +1.604.822.2872
Fax +1.604.822.5949
Email:

Emergency Procedures | Accessibility | Contact UBC | © Copyright 2021 The University of British Columbia