Implementing logic in FPGA memory arrays: heterogeneous memory architectures

TitleImplementing logic in FPGA memory arrays: heterogeneous memory architectures
Publication TypeConference Paper
Year of Publication2002
AuthorsWilton, S. J. E.
Conference NameField-Programmable Technology, 2002. (FPT). Proceedings. 2002 IEEE International Conference on
Pagination142 - 147
Date Publisheddec.
Keywords128 bit, 2048 bit, field programmable gate arrays, FPGA memory arrays, heterogeneous memory architectures, integrated memory circuits, large embedded configurable memory arrays, memory architecture, onchip storage
Abstract

It has become clear that large embedded configurable memory arrays will be essential in future FPGAs. Embedded arrays provide high-density high-speed implementations of the storage parts of circuits. Unfortunately, they require the FPGA vendor to partition the device into memory and logic resources at manufacture-time. This leads to a waste of chip area for customers that do not use all of the storage provided This chip area need not be wasted, and can in fact be used very efficiently, if the arrays are configured as large multi-output ROMs, and used to implement logic. In this paper we investigate how the architecture of the FPGA embedded arrays affects their ability to implement logic. Specifically, we focus on architectures which contain more than one size of memory array. We show that these heterogeneous architectures result in significantly denser implementations of logic than architectures with only one size of memory array. We also show that the best heterogeneous architecture contains both 2048 bit arrays and 128 bit arrays.

URLhttp://dx.doi.org/10.1109/FPT.2002.1188675
DOI10.1109/FPT.2002.1188675

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