The memory/logic interface in FPGAs with large embedded memory arrays

TitleThe memory/logic interface in FPGAs with large embedded memory arrays
Publication TypeJournal Article
Year of Publication1999
AuthorsWilton, S. J. E., J. Rose, and Z. G. Vranesic
JournalVery Large Scale Integration (VLSI) Systems, IEEE Transactions on
Volume7
Pagination80 -91
Date Publishedmar.
ISSN1063-8210
Keywordscellular arrays, chip area, circuit layout CAD, embedded systems, field programmable gate arrays, FPGAs, large embedded memory arrays, logic CAD, logic resources, memory access time, memory/logic interface, multiple memory arrays, network routing, reconfigurable architectures, routing structure, routing tracks, storage requirements
Abstract

As the capacities of field-programmable gate arrays (FPGAs) grow, they will be used to implement much larger circuits than ever before. These larger circuits often require significant amounts of storage. In order to address these storage requirements, FPGAs with large embedded memory arrays are now being developed by several vendors. One of the crucial components of an FPGA with on-chip memory is the routing structure between the memory arrays and logic resources. If this memory/logic interface is not flexible enough, many circuits will be unroutable, while if it is too flexible, it will be slower and consume more chip area than is necessary. In this paper, we show that an interconnect in which each memory pin can connect to between four and seven logic routing tracks is best in terms of both area and speed. We also show that by adding switches to support nets that connect multiple memory arrays, we can reduce the memory access time by up to 25% and improve the routability slightly

URLhttp://dx.doi.org/10.1109/92.748203
DOI10.1109/92.748203

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