Implementing logic in FPGA embedded memory arrays: architectural implications

TitleImplementing logic in FPGA embedded memory arrays: architectural implications
Publication TypeConference Paper
Year of Publication1998
AuthorsWilton, S. J. E.
Conference NameCustom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998
Pagination269 -272
Date Publishedmay.
Keywords512 to 2048 bit, architectural implications, array size, array width, field programmable gate arrays, FPGA embedded memory arrays, logic design, memory architecture, read-only storage, ROM

It has become clear that embedded memory arrays will be essential in future FPGAs. These arrays were originally intended to implement storage, but recent work has shown that they can also be used to implement logic very efficiently. In this paper, we explore how the depth, width, and flexibility of the embedded arrays affect their ability to implement logic. It is shown that each array should contain between 512 and 2048 bits, and should have a word width that can be configured as 1, 2, 4, or 8


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