Memory/logic interconnect flexibility in FPGAs with large embedded memory arrays

TitleMemory/logic interconnect flexibility in FPGAs with large embedded memory arrays
Publication TypeConference Paper
Year of Publication1996
AuthorsWilton, S. J. E., J. Rose, and Z. G. Vrancsic
Conference NameCustom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996
Pagination144 -147
Date Publishedmay.
Keywordscellular arrays, delay, delays, embedded memory arrays, field programmable gate arrays, FPGAs, integrated circuit interconnections, logic CAD, logic connection block, memory/logic interconnect flexibility, network routing, routability

As the capacities of field-programmable gate arrays (FPGAs) grow, it becomes desirable to create FPGAs with embedded memory arrays. This paper examines the flexibility of the interconnect structure that joins memory and logic. For architectures with only a few memory arrays, we find that both the routability and the delay of circuits are insensitive to the memory/logic interconnect flexibility, which implies that this interconnection can be made very inflexible. This is in contrast to the logic connection block flexibility, which has been shown to require high flexibility. For architectures with more arrays, the memory/logic interconnect flexibility requirements increase and approach those of logic interconnect


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