SRAM retention testing: zero incremental time integration with March algorithms

TitleSRAM retention testing: zero incremental time integration with March algorithms
Publication TypeConference Paper
Year of Publication2005
AuthorsWang, B., Y. Wu, J. Yang, A. Ivanov, and Y. Zorian
Conference NameVLSI Test Symposium, 2005. Proceedings. 23rd IEEE
Pagination66 - 71
Date Publishedmay.
Keywordsdata retention fault testing, embedded SRAM, fault diagnosis, integrated circuit testing, March algorithms, memory cells, memory design, PDWTM, predischarge write test mode, SRAM chips, SRAM retention testing, system on chip, system-on-chip, zero incremental time integration, zero-time DRF testing

Testing data retention faults (DRFs), particularly in integrated systems on chip comprised of very large number of various sizes and types of embedded SRAMs is challenging and typically time-consuming due to the required pause time that needs to be introduced in the test session. This paper proposes a novel technique, referred to as pre-discharge write test mode (PDWTM), that effectively integrates the testing of DRF within "regular" March algorithms such that the rate (speed) of the latter remains unaltered. That is, the PDWTM enables DRF testing without incurring the additional cycles or pauses in the March test execution thereby enabling additional coverage at no expense in terms of overall test time. We show that DRFs can be easily detected by pre-discharging bit lines before a write operation. Here, the PDWTM is evaluated using both high-speed and low power memory cells, representing two extreme cases based on the typical memory design methodologies.


a place of mind, The University of British Columbia

Electrical and Computer Engineering
2332 Main Mall
Vancouver, BC Canada V6T 1Z4
Tel +1.604.822.2872
Fax +1.604.822.5949

Emergency Procedures | Accessibility | Contact UBC | © Copyright 2021 The University of British Columbia