A retention-aware test power model for embedded SRAM

TitleA retention-aware test power model for embedded SRAM
Publication TypeConference Paper
Year of Publication2005
AuthorsWang, B., J. Yang, Y. Wu, and A. Ivanov
Conference NameDesign Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Pagination1180 - 1183 Vol. 2
Date Publishedjan.
Keywordsdata retention fault test, data retention faults, e-SRAM, embedded SRAM, embedded systems, integrated circuit modelling, integrated circuit testing, logic testing, memory capacities, optimisation, retention test duration, scheduling, SoC core, SRAM chips, system-on-chip, test algorithm complexities, test power consumption, test power model, test scheduling, test time reduction
Abstract

This paper addresses the test power model problem for embedded SRAMs (e-SRAMs). Previous researches treat e-SRAMs the same as other SoC core and use a "single-rectangle" power model to describe their test power consumption. This leads to significant waste of test time since e-SRAM test usually includes a long period of "zero" power consumption for the detection of data retention faults, This paper takes advantage of this "zero" power period and proposes a "retention-aware" test power model for e-SRAMs. The proposed model is evaluated and its impact on test time reduction is reported for various scenarios in terms of retention test duration, memory capacities, test algorithm complexities, etc. A formula is derived to predict the maximum test time reduction when the "zero" power period is fully utilized in a SoC environment.

URLhttp://dx.doi.org/10.1109/ASPDAC.2005.1466552
DOI10.1109/ASPDAC.2005.1466552

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