Designs for reducing test time of distributed small embedded SRAMs

TitleDesigns for reducing test time of distributed small embedded SRAMs
Publication TypeConference Paper
Year of Publication2004
AuthorsWang, B., Y. Wu, and A. Ivanov
Conference NameDefect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on
Pagination120 - 128
Date Publishedoct.
Keywordsdata retention faults, defect coverage, design for testability, DFT technique, distributed small embedded SRAM, DRF, e-SRAM, integrated circuit testing, logic testing, LRA, no write recovery test mode, parallel local response analyzer, SoC, SRAM chips, SRAM test time reduction, test architecture, XWRTM

This paper proposes a test architecture aimed at reducing test time of distributed small embedded SRAMs (e-SRAMs). This architecture improves the one proposed in (W. B. Jone et al, Proc. 17th IEEE VLSI Test Symp., p.246- 251, 1999 and also IEEE Transact. VLSI Syst., vol.10, no.4, p.512-515, 2002). The improvements are mainly two-fold. On one hand, the testing of time-consuming data retention faults (DRFs), that is neglected by the previously proposed test architecture, is now considered and performed via a DFT technique referred to as the "no write recovery test mode (XWRTM)". On the other hand, a parallel local response analyzer (LRA), instead of a serial response analyzer, is used to reduce the test time of these distributed small e-SRAMs. Results from our evaluations show that the proposed test architecture can achieve a better defect coverage and test time compared to those obtained previously, with a negligible area cost.


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