Yield, overall test environment timing accuracy, and defect level trade-offs for high-speed interconnect device testing

TitleYield, overall test environment timing accuracy, and defect level trade-offs for high-speed interconnect device testing
Publication TypeConference Paper
Year of Publication2003
AuthorsWang, B., Y. B. Cho, S. Tabatabaei, and A. Ivanov
Conference NameTest Symposium, 2003. ATS 2003. 12th Asian
Pagination348 - 353
Date Publishednov.
Keywordsdefect level trade-offs, electronic equipment testing, high-speed interconnect device testing, HyperTransport, interconnections, OTETA, overall test environment timing accuracy, PCI Express, RapidIO, test equipment, test fixture effects, tester OTA, testing yield, timing, timing specifications testing, yield analysis, yield defect level
Abstract

This paper extends the model in (Wajih Dalai et al, Proc. of Int. Test Conf., p.518-523, 1999) to be more realistic by including the effects of the test fixtures between a device under test and a tester. The paper enables analyzing the trade-offs that arise between the predicted yield and the required overall test environment timing accuracy (OTETA) which involves the tester overall timing accuracy (OTA) and the test fixture impact. We specifically focus on the application of the extended model to predict the test yield of standard high-speed interconnects, such as PCI Express, RapidIO, and HyperTransport. The extended model reveals that achieving an actual yield of 80% with a defect level of 300 DPM (defects per million) requires an equivalent OTETA that is about half the acceptable absolute limit of the tested parameter.

URLhttp://dx.doi.org/10.1109/ATS.2003.1250835
DOI10.1109/ATS.2003.1250835

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