Reducing test time of embedded SRAMs

TitleReducing test time of embedded SRAMs
Publication TypeConference Paper
Year of Publication2003
AuthorsWang, B., J. Yang, and A. Ivanov
Conference NameMemory Technology, Design and Testing, 2003. Records of the 2003 International Workshop on
Pagination47 - 52
Date Publishedjul.
Keywordsdefect level, defect simulations, detecting data retention faults, embedded SRAM, embedded systems, failure analysis, fault modeling, functional fault models, inductive fault analysis test flow, memory redundancy elements, redundancy, SRAM capacity, SRAM chips, surging test time, synchronous random access memory, test algorithm, test generation algorithm, test quality, test time reduction, timing

Compared with traditional functional fault models, fault model obtained from an Inductive Fault Analysis (IFA) test flow can provide an attractive basis for obtaining a good estimate of the overall test quality in terms of defect level and yield. However, the associated surging test time due to increased SRAM capacity is becoming a major challenge when testing either standalone or embedded SRAMs. This paper refines the functional fault models translated from defect simulations for embedded SRAMs with IFA proposed and described. Reconsidering the defect causes of the functional faults allows us to simplify the functional fault model FFM2 and formulate the test time required for detecting Data Retention Faults. We combine this simplification with the consideration of specific memory redundancy elements to develop a new March 6N Test algorithm. Simulation results reveal that our proposed fault modeling and test generation algorithm can reduce total test time to one half or less of that required by the methodology, while maintaining the same defect and fault coverage.


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