Computer arithmetic structures for quantum cellular automata

TitleComputer arithmetic structures for quantum cellular automata
Publication TypeConference Paper
Year of Publication2003
AuthorsWalus, K., G. A. Jullien, and V. S. Dimitrov
Conference NameSignals, Systems and Computers, 2003. Conference Record of the 37th Asilomar Conference on
Pagination1435 - 1439 Vol.2
Date Publishednov.
Keywordsadders, addition circuit, arithmetic structure, boolean gate, cellular automata, computational architecture, cost function, delays, device level latching, flip-flops, multiplication circuit, multiplying circuits, quantum cellular automata, standard transistor circuit, transistor circuits
Abstract

In this paper, we discuss arithmetic structures based on quantum cellular automata (QCA). By taking advantage of the unique capabilities of QCA we are able to design interesting computational architectures. We describe important design considerations and show how addition and multiplication circuits can be implemented using QCADesigner, a QCA design tool which has been developed in our laboratory. QCA technology allows, among other things, the implementation of majority boolean gates and interconnecting "wires" that support cross-overs on the same fabrication level. One of the important challenges with QCA design is working within a different cost function from standard transistor circuits. These differences arise from the device level latching inherent in QCA. This latching makes the total delay of a circuit directly proportional to the maximum number of clocking zones between input and output and the number of gates.

URLhttp://dx.doi.org/10.1109/ACSSC.2003.1292223
DOI10.1109/ACSSC.2003.1292223

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