An efficient systolic array implementation of the sign-LMS algorithm

TitleAn efficient systolic array implementation of the sign-LMS algorithm
Publication TypeJournal Article
Year of Publication1992
AuthorsViriato, L. A., and T. Aboulnasr
JournalCircuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
Pagination322 -325
Date Publishedmay.
Keywords2D convolver array, bit-level systolic array, coefficients updating, computerised signal processing, digital signal processing chips, least squares approximations, linear updater array, sign-LMS algorithm, systolic array implementation, systolic arrays

A bit-level systolic array of the implementation of the LMS algorithm is presented. The array is divided into a 2D convolver array and a linear updater array. The structure is 100% data flow efficient, requiring N/2 rows to implement N coefficients. The updater is made up of N/2 simple cells. The sign-LMS algorithm is used for updating the coefficients. All coefficients are updated every 2R clocks where R is the number of bits per coefficient and the clock is the bit-level clock (array clock)


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