Logic block clustering of large designs for channel-width constrained FPGAs

TitleLogic block clustering of large designs for channel-width constrained FPGAs
Publication TypeConference Paper
Year of Publication2005
AuthorsTom, M., and G. Lemieux
Conference NameDesign Automation Conference, 2005. Proceedings. 42nd
Pagination726 - 731
Date Publishedjun.
Keywordschannel width area reduction, circuit routing, CLB count, CLB inflation, field programmable gate arrays, field-programmable gate arrays, FPGA channel width, FPGA clustering tools, hard-to-route regions, intercluster connections, logic block clustering, logic clusters, multiple-IP-block designs, nonuniform depopulation, programmable circuits, routable solutions, system level technique, unroutable circuits
Abstract

In this paper we present a system level technique for mapping large, multiple-IP-block designs to channel-width constrained FPGAs. Most FPGA clustering tools (Betz, 1999, Bozorgzadeh, 2004 and Singh, 2002) aim to reduce the amount of intercluster connections, hence reducing channel width needs. However, if this exceeds the FPGA's channel width (a hard constraint), then the circuit still cannot be routed. Previous work by Singh (2002) and Tessier (2000) depopulates logic clusters (CLBs) to reduce channel width. By depopulating non-uniformly, i.e. depopulate more in hard-to-route regions, we show a graceful trade-off between channel width and CLB count. This makes it possible to target specific channel-width constraints during clustering with minimal CLB inflation. Results show channel width decreases of up to 20% with a 5% increase in area. Further decreases of nearly 50% are possible at 3.3 times the original area. Despite the area increase, this technique creates routable solutions from otherwise unroutable circuits.

URLhttp://dx.doi.org/10.1109/DAC.2005.193907
DOI10.1109/DAC.2005.193907

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