A Survey and Taxonomy of GALS Design Styles

TitleA Survey and Taxonomy of GALS Design Styles
Publication TypeJournal Article
Year of Publication2007
AuthorsTeehan, P., M. Greenstreet, and G. Lemieux
JournalDesign Test of Computers, IEEE
Pagination418 -428
Date Publishedsep.
Keywordsasynchronous interconnect, clocking requirements, digital circuits, GALS design, globally asynchronous, interblock communication, large SoC designs, locally synchronous, logic design, multiple clock domain, single-clocked digital systems

Single-clocked digital systems are largely a thing of the past. Although most digital circuits remain synchronous, many designs feature multiple clock domains, often running at different frequencies. Using an asynchronous interconnect decouples the timing issues for the separate blocks. Systems employing such schemes are called globally asynchronous, locally synchronous (GALS). To minimize time to market, large SoC designs must integrate many functional blocks with minimal design effort. These blocks are usually designed using standard synchronous methods and often have different clocking requirements. A GALS approach can facilitate fast block reuse by providing wrapper circuits to handle interblock communication across clock domain boundaries. SoCs may also achieve power savings by clocking different blocks at their minimum speeds. For example, Scott et al. describe the advantages of GALS design for an embedded-processor peripheral bus.


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