Simulation of a dual gate organic transistor compatible with printing methods

TitleSimulation of a dual gate organic transistor compatible with printing methods
Publication TypeJournal Article
Year of Publication2008
AuthorsTakshi, A., A. Dirnopoulos, and J. D. Madden
JournalSolid -State Electronics
Volume52
Pagination107–114
ISSN0038-1101
Abstract

In fabricating organic field-effect transistors (OFET) the deposition of a very thin and electrically Continuous semiconductor layer using a low-cost process such as a printing method is a challenge. A simple model is proposed which relates performance to thickness, and shows that the thick layers typical of low-cost methods lead to poor device properties. The analytical model of thickness dependence is shown to match OFET simulation results for a range of thickness. These results indicate a change in the threshold voltage and drops in the Output impedance and the current ratio with an increase in the semiconductor thickness. As a solution a dual gate structure is suggested for organic transistors, in which the secondary gate controls the effective thickness of the organic layer through a Schottky contact with the semiconductor. Simulation results for a 200 nm thick dual gate OFET show a performance much better than is observed in a near optimal 20 nm thick OFET, by achievement of a current ratio of 10(6), versus 2500 in the OFET. (C) 2007 Elsevier Ltd. All rights reserved.

URLhttp://dx.doi.org/10.1016/j.sse.2007.07.011
DOI10.1016/j.sse.2007.07.011

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