Embedded timing analysis: A SoC infrastructure

TitleEmbedded timing analysis: A SoC infrastructure
Publication TypeJournal Article
Year of Publication2002
AuthorsTabatabaei, S., and A. Ivanov
JournalIEEE Design & Test of Computers
Volume19
Pagination24–36
ISSN0740-7475
Abstract

This SoC infrastructure core is a flexible, scalable, and highly accurate embedded time interval analyzer (ETIA), used to measure a variety of timing-related SoC characteristics, including jitter. The ETIA requires little design and area overhead and performs accurately under process and environment variation and noise.

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