A versatile time-domain Reed-Solomon decoder

TitleA versatile time-domain Reed-Solomon decoder
Publication TypeJournal Article
Year of Publication1990
AuthorsShayan, Y. R., T. Le-Ngoc, and V. K. Bhargava
JournalSelected Areas in Communications, IEEE Journal on
Volume8
Pagination1535 -1542
Date Publishedoct.
ISSN0733-8716
Keywords1.5 micron, CMOS integrated circuits, decoding, error correction codes, Galois field, logic arrays, time-domain Reed-Solomon decoder, time-domain synthesis, two-layer-metal HCMOS, VLSI, VLSI gate-array-based decoder
Abstract

A versatile Reed-Solomon (RS) decoder structure based on the time-domain decoding algorithm (transform decoding without transforms) is developed. The algorithm is restructured, and a method is given to decode any RS code generated by any generator polynomial. The main advantage of the decoder structure is its versatility, that is, it can be programmed to decode any Reed-Solomon code defined in Galois field (GF) 2m with a fixed symbol size m. This decoder can correct errors and erasures for any RS code, including shortened and singly extended codes. It is shown that the decoder has a very simple structure and can be used to design high-speed single-chip VLSI decoders. As an example, a gate-array-based programmable RS decoder is implemented on a single chip. This decoder chip can decode any RS code defined in GF (25) with any code word length and any number of information symbols. The decoder chip is fabricated using low-power 1.5- mu;, two-layer-metal, HCMOS technology

URLhttp://dx.doi.org/10.1109/49.62831
DOI10.1109/49.62831

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