Application-driven floorplan-aware voltage island design

TitleApplication-driven floorplan-aware voltage island design
Publication TypeConference Paper
Year of Publication2008
AuthorsSengupta, D., and R. Saleh
Conference NameDesign Automation Conference, 2008. DAC 2008. 45th ACM/IEEE
Pagination155 -160
Date Publishedjun.
Keywordsdynamic programming, floorplan-aware voltage island design, integrated circuit layout, power state model, system-on-chip, system-on-chip designs, voltage island technique
Abstract

Among the different methods of reducing power for core-based system-on-chip (SoC) designs, the voltage island technique has gained in popularity. Assigning cores to the different supply voltages and floorplanning to create contiguous voltage islands are the two important steps in the design process. We propose a new application-driven, floorplan-aware approach to voltage partitioning and island creation with the objective of reducing overall SoC power, area and runtime. Previous approaches used the voltage assignment table as the starting point for voltage island creation. In this paper, we present a technique to generate a voltage assignment table using dynamic programming. Next, we partition the cores into islands, based on the Power State Model (PSM) of the application, and connectivity information used in floorplanning. Finally, solutions are sent to the floorplanner in sequence until a valid solution is reached. Compared to previously reported techniques, a 10% reduction in power and 8% reduction in area are achieved using our approach, with an average runtime improvement of 2.3X.

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