Generalized Power-Delay Metrics in Deep Submicron CMOS Designs

TitleGeneralized Power-Delay Metrics in Deep Submicron CMOS Designs
Publication TypeJournal Article
Year of Publication2007
AuthorsSengupta, D., and R. Saleh
JournalComputer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Volume26
Pagination183 -189
Date Publishedjan.
ISSN0278-0070
KeywordsCMOS integrated circuits, deep submicron CMOS designs, energy-delay product, leakage currents, nanotechnology, power reduction, power-delay metrics, SoC, system-on-chip, very-large-scale integration, VLSI
Abstract

Recently, designers have been using the energy-delay product as a metric of goodness for CMOS designs due to certain perceived shortcomings of the more traditional power-delay product. As the industry moves to 90-nm technology with higher leakage currents, it is appropriate to revisit existing design metrics. In this paper, a reevaluation of the metrics is carried out, and a generalized set of metrics is proposed. Supply voltage (VDD) and threshold voltage (VT) scaling are two popular approaches to power reduction. As such, the effects on power and frequency are analyzed, and the feasible region of operation is identified in the VDD versus VT plane. A fundamental relationship is established between the optimal operating points and the generalized design metrics. The initial findings also indicate that some designs may have a higher percentage of leakage than expected to achieve overall power reduction, running somewhat counter to conventional wisdom

URLhttp://dx.doi.org/10.1109/TCAD.2006.883926
DOI10.1109/TCAD.2006.883926

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