A fully differential high-speed double-edge triggered flip-flop (DETFF)

TitleA fully differential high-speed double-edge triggered flip-flop (DETFF)
Publication TypeConference Paper
Year of Publication2004
AuthorsSameni, P., and S. Mirabbasi
Conference NameElectrical and Computer Engineering, 2004. Canadian Conference on
Pagination1459 - 1462 Vol.3
Date Publishedmay.
Keywords0.18 micron, 0.8 V, 1.8 V, 25 Gbit/s, 7 mW, clock rate, CMOS digital integrated circuits, CMOS technology, data rate, differential flip-flop, differential high-speed double-edge triggered flip-flop, differential output swing, flip-flops, high-speed flip-flop, high-speed integrated circuits, integrated circuit design, power consumption

A high-speed double-edge-triggered flip-flop designed in 0.18 mu;m CMOS technology is presented. Flip-flops, to a large extent, determine the speed of synchronous systems. The proposed flip-flop can operate with a clock rate as high as 12.5 GHz, which translates to 25 Gb/s data rate. It samples the data on both edges of the clock. All signals are realized differentially. The differential output swing is 0.8 V with a 1.8 V power supply. The average power consumption is 7 mW. A performance comparison between the proposed flip-flop and a single-edge triggered flip-flop realized in the same technology is also presented.


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