A 1/8-rate clock and data recovery architecture for high-speed communication systems

TitleA 1/8-rate clock and data recovery architecture for high-speed communication systems
Publication TypeConference Paper
Year of Publication2004
AuthorsSameni, P., and S. Mirabbasi
Conference NameCircuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
PaginationIV - 305-8 Vol.4
Date Publishedmay.
Keywords40 Gbit/s, 5 GHz, clock rate reduction, clock recovery architecture, CMOS digital integrated circuits, data recovery architecture, data transition density, deep submicron CMOS designs, demultiplexing, encounters, high-speed communication systems, high-speed integrated circuits, integrated circuit design, integrated circuit modelling, multiphase VCO, multiphase voltage-controlled oscillator, optical communication, optical communication system, synchronisation, voltage-controlled oscillators
Abstract

A new clock and data recovery (CDR) architecture for high-speed communication applications is introduced. The proposed CDR architecture is described in the context of a 40-Gb/s optical communication system. This architecture utilizes 1/8-rate clock to recover and demultiplex the data, and it does not require a frequency divider. Also, the CDR system employs a rate-reduction block to lower the data transition density and thereby alleviates the speed requirements of the data recovery process. For a 40-Gb/s system, the CDR uses a multiphase voltage-controlled oscillator (VCO) with 5-GHz center frequency. The proposed architecture is particularly suitable for deep submicron CMOS designs where the designer encounters difficulties in implementing a full-rate clock and data recovery.

URLhttp://dx.doi.org/10.1109/ISCAS.2004.1329001
DOI10.1109/ISCAS.2004.1329001

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