Trends in low power digital System-On-Chip designs

TitleTrends in low power digital System-On-Chip designs
Publication TypeConference Paper
Year of Publication2002
AuthorsSaleh, R., G. Lim, T. Kadowaki, and K. Uchiyama
Conference NamePROCEEDING OF THE 2002 3RD INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN
Pagination373-378
PublisherIEEE Tech Comm VLSI Design; IEEE Comp Soc Tech Comm Design Automat; IEEE Comp Soc Test Technol Tech Council; IEEE Electron Devices Soc; Fabless Semicond Assoc; ACM/sigDA
Conference Location10662 LOS VAQUEROS CIRCLE, PO BOX 3014, LOS ALAMITOS, CA 90720-1264 USA
ISBN Number0-7695-1562-2
Abstract

A study of the future trends in low-power System-on-Chip (SOC) designs is presented, based on the recently announced ITRS-2001 technology characteristics for both high-performance and low-power devices from 2001 to 2016. We forecast the logic/memory composition of a reference low-power PDA design with an area constraint of 1 cm(2) using both a bottom-up, power dissipation-constrained chip model and a top-down, design resource-constrained model. Together, these analyses indicate that without accelerated improvements in both chip design productivity and leakage power management, future SOC designs will be comprised of 80-90% memory, with the remaining logic blocks composed of special-purpose reusable IP cores, and a smaller fraction of the chip containing newly designed logic.

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