Full-chip verification of UDSM designs

TitleFull-chip verification of UDSM designs
Publication TypeConference Paper
Year of Publication1998
AuthorsSaleh, R., D. OVERHAUSER, and S. Taylor
Conference Name1998 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN - DIGEST OF TECHNICAL PAPERS
Pagination453-460
PublisherIEEE, Circuits & Syst Soc; IEEE, Comp Soc; Assoc Comp Machinery, Special Interest Grp Design Autmat
Conference Location1515 BROADWAY, NEW YORK, NY 10036-9998 USA
ISBN Number1-58113-008-2
Abstract

This tutorial describes the problems encountered in typical ultra-deep submicron (UDSM) designs, and the full-chip interconnect verification methodologies needed to successfully identify these problems before tape-out. We first illustrate that UDSM verification must go well beyond simple geometric and circuit comparison checks to address increasingly important issues such as timing, power integrity, signal integrity, and reliability. The key issues of IR drops in the power grid, electromigration in power and signal lines, clock skew, signal coupling and its effect on timing and noise are described. We present real-world examples of such problems and how to find these problems using full-chip verification.

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