Testing for floating gates defects in CMOS circuits

TitleTesting for floating gates defects in CMOS circuits
Publication TypeConference Paper
Year of Publication1998
AuthorsRafiq, S., A. Ivanov, S. Tabatabaei, and M. Renovell
Conference NameTest Symposium, 1998. ATS '98. Proceedings. 7th Asian
Pagination228 -236
Date Publisheddec.
Keywordsabnormal logic values, Boolean functions, CMOS circuits, CMOS logic circuits, delays, detectability intervals, dynamic voltage, fault diagnosis, floating gates defects, logic testing, predictable parameters, static current, static voltage, unpredictable parameters, voltage testing strategies
Abstract

This paper studies the detectability of MOS floating gate transistor faults considering classical static voltage, dynamic voltage and static current strategies. The behavior of the defect depends on two classes of parameters: the predictable and unpredictable parameters. A floating gate fault can induce abnormal logic values, additional delays, or increased power supply current. Consequently, classical test strategies can only detect floating gate faults for a given range of the unpredictable parameter. Here, a new test scheme is proposed, which allows a considerable current to flow in the stable state making the circuit with a floating gate IDDQ testable. It is shown that a combination of voltage and current testing can ensure 100% detection of the floating gate defects, i.e., regardless of the unpredictable parameters. Analysis with increasing initial charge on the floating gate transistor shows how the detectability intervals become smaller for the voltage testing strategies and increase for the static current strategy

URLhttp://dx.doi.org/10.1109/ATS.1998.741618
DOI10.1109/ATS.1998.741618

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